Add driver for VSC9953 Ethernet Switch

index f1e39b9..1d1089d 100644
@@ -410,10 +410,15 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 	fmc_tx_port_graceful_stop_disable(fm_eth);
 
 #ifdef CONFIG_PHYLIB
-	ret = phy_startup(fm_eth->phydev);
-	if (ret) {
-		printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
-		return ret;
+	if (fm_eth->phydev) {
+		ret = phy_startup(fm_eth->phydev);
+		if (ret) {
+			printf("%s: Could not initialize\n",
+			       fm_eth->phydev->dev->name);
+			return ret;
+		}
+	} else {
+		return 0;
 	}
 #else
 	fm_eth->phydev->speed = SPEED_1000;

@@ -447,7 +452,8 @@ static void fm_eth_halt(struct eth_device *dev)
 	/* disable bmi Rx port */
 	bmi_rx_port_disable(fm_eth->rx_port);
 
-	phy_shutdown(fm_eth->phydev);
+	if (fm_eth->phydev)
+		phy_shutdown(fm_eth->phydev);
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)

@@ -625,11 +631,12 @@ static int init_phy(struct eth_device *dev)
 	if (fm_eth->bus) {
 		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
 					fm_eth->enet_if);
-	}
-
-	if (!phydev) {
-		printf("Failed to connect\n");
-		return -1;
+		if (!phydev) {
+			printf("Failed to connect\n");
+			return -1;
+		}
+	} else {
+		return 0;
 	}
 
 	if (fm_eth->type == FM_ETH_1G_E) {

@@ -711,8 +718,7 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 	if (!fm_eth_startup(fm_eth))
 		return 0;
 
-	if (init_phy(dev))
-		return 0;
+	init_phy(dev);
 
 	/* clear the ethernet address */
 	for (i = 0; i < 6; i++)

index 5cfae47..f8e6c00 100644
@@ -15,16 +15,16 @@
 #include "fsl_corenet2_serdes.h"
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-static u64 serdes1_prtcl_map;
+static int serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-static u64 serdes2_prtcl_map;
+static int serdes2_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-static u64 serdes3_prtcl_map;
+static int serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-static u64 serdes4_prtcl_map;
+static int serdes4_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
 #ifdef DEBUG

@@ -83,19 +83,19 @@ static const char *serdes_prtcl_str[] = {
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-	u64 ret = 0;
+	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	ret |= (1ULL << device) & serdes1_prtcl_map;
+	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	ret |= (1ULL << device) & serdes2_prtcl_map;
+	ret |= serdes2_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-	ret |= (1ULL << device) & serdes3_prtcl_map;
+	ret |= serdes3_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-	ret |= (1ULL << device) & serdes4_prtcl_map;
+	ret |= serdes4_prtcl_map[device];
 #endif
 
 	return !!ret;

@@ -171,12 +171,14 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 #define BCAP_OVD_MASK		0x10000000
 #define BYP_CAL_MASK		0x02000000
 
-u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		int serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 	struct ccsr_sfp_regs  __iomem *sfp_regs =
 			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);

@@ -312,38 +314,40 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
-		serdes_prtcl_map |= (1ULL << lane_prtcl);
+		serdes_prtcl_map[lane_prtcl] = 1;
 	}
-
-	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_2,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
+		    serdes2_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_3,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
+		    serdes3_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-	serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_4,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
+		    serdes4_prtcl_map);
 #endif
 
 }

index 8e0e190..2dd32c2 100644
@@ -87,6 +87,7 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	SERDES_PRCTL_COUNT	/* Keep this item the last one */
 };
 
 enum srds {

index f8e6c00..03c4642 100644
@@ -78,6 +78,12 @@ static const char *serdes_prtcl_str[] = {
 	[INTERLAKEN] = "INTERLAKEN",
 	[QSGMII_SW1_A] = "QSGMII_SW1_A",
 	[QSGMII_SW1_B] = "QSGMII_SW1_B",
+	[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
+	[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
+	[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
+	[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
+	[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
+	[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
 };
 #endif
 

index d86bb27..d5dccd5 100644
@@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
 		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-	[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
-		PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
-	[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
-		PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
+	[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+		PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
+	[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+		PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
 	[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

index 2dd32c2..45e248e 100644
@@ -87,6 +87,12 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	SGMII_SW1_MAC1,
+	SGMII_SW1_MAC2,
+	SGMII_SW1_MAC3,
+	SGMII_SW1_MAC4,
+	SGMII_SW1_MAC5,
+	SGMII_SW1_MAC6,
 	SERDES_PRCTL_COUNT	/* Keep this item the last one */
 };
 

index d2a097e..0458366 100644
@@ -50,7 +50,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	switch (port) {
 	case FM1_DTSEC1:
 	case FM1_DTSEC2:
-		if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
+		if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
+		    is_serdes_configured(SGMII_SW1_MAC1  + port - FM1_DTSEC1))
 			return PHY_INTERFACE_MODE_QSGMII;
 	case FM1_DTSEC3:
 	case FM1_DTSEC4:

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402 lines not on this page · raw message

index 2d28eb2..41026d1 100644
@@ -15,6 +15,9 @@
 #include <netdev.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#ifdef CONFIG_VSC9953
+#include <vsc9953.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -271,5 +274,9 @@ int cpu_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
 	fm_standard_init(bis);
 #endif
+
+#ifdef CONFIG_VSC9953
+	vsc9953_init(bis);
+#endif
 	return 0;
 }

index 01b0905..79caac1 100644
@@ -747,6 +747,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1020)
+#define CONFIG_VSC9953			/* Vitesse L2 Switch */
+#endif
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #endif

index 06d9086..c6fc146 100644
@@ -216,6 +216,7 @@ static void initialize_lane_to_slot(void)
 		lane_to_slot[1] = 7;
 		lane_to_slot[2] = 7;
 		lane_to_slot[3] = 7;
+		lane_to_slot[6] = 7;
 		lane_to_slot[7] = 7;
 		break;
 	case 0x8d:

index c6fc146..2f8e753 100644
@@ -478,6 +478,7 @@ int board_eth_init(bd_t *bis)
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_mdio(i, NULL);
 			break;
 		case PHY_INTERFACE_MODE_SGMII:
 			t1040_handle_phy_interface_sgmii(i);

index c8b6c67..f5c0ec8 100644
@@ -72,8 +72,13 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_phy_address(i, 0);
 			break;
 		}
-		fm_info_set_mdio(i,
-				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+			fm_info_set_mdio(i, NULL);
+		else
+			fm_info_set_mdio(i,
+					 miiphy_get_dev_by_name(
+							DEFAULT_FM_MDIO_NAME));
 	}
 
 	cpu_eth_init(bis);

index 2f8e753..ba6f518 100644
@@ -18,6 +18,9 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#ifdef CONFIG_VSC9953
+#include <vsc9953.h>
+#endif
 
 #include "../common/fman.h"
 #include "../common/qixis.h"

@@ -439,6 +442,12 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
 	struct memac_mdio_info memac_mdio_info;
 	unsigned int i;
+#ifdef CONFIG_VSC9953
+	int lane;
+	int phy_addr;
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
 
 	printf("Initializing Fman\n");
 	set_brdcfg9_for_gtx_clk();

@@ -493,6 +502,90 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+#ifdef CONFIG_VSC9953
+	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+		lane = -1;
+		phy_addr = 0;
+		phy_int = PHY_INTERFACE_MODE_NONE;
+		switch (i) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
+			/* PHYs connected over QSGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
+						i;
+				phy_int = PHY_INTERFACE_MODE_QSGMII;
+				break;
+			}
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_SW1_MAC1 + i);
+
+			if (lane < 0)
+				break;
+
+			/* PHYs connected over QSGMII */
+			if (i != 3 || lane_to_slot[lane] == 7)
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+					+ i;
+			else
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
+			phy_int = PHY_INTERFACE_MODE_SGMII;
+			break;
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
+			/* PHYs connected over QSGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
+						i - 4;
+				phy_int = PHY_INTERFACE_MODE_QSGMII;
+				break;
+			}
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_SW1_MAC1 + i);
+			/* PHYs connected over SGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+						+ i - 3;
+				phy_int = PHY_INTERFACE_MODE_SGMII;
+			}
+			break;
+		case 8:
+			if (serdes_get_first_lane(FSL_SRDS_1,
+						  SGMII_FM1_DTSEC1) < 0)
+				/* FM1 at DTSEC1 is connected to SW1@PORT8 */
+				vsc9953_port_enable(i);
+			break;
+		case 9:
+			if (serdes_get_first_lane(FSL_SRDS_1,
+						  SGMII_FM1_DTSEC2) < 0) {
+				/* Enable L2 On MAC2 using SCFG */
+				struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+						CONFIG_SYS_MPC85xx_SCFG;
+
+				out_be32(&scfg->esgmiiselcr,
+					 in_be32(&scfg->esgmiiselcr) |
+					 (0x80000000));
+				vsc9953_port_enable(i);
+			}
+			break;
+		}
+
+		if (lane >= 0) {
+			bus = mii_dev_for_muxval(lane_to_slot[lane]);
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_enable(i);
+		}
+		vsc9953_port_info_set_phy_address(i, phy_addr);
+		vsc9953_port_info_set_phy_int(i, phy_int);
+	}
+
+#endif
 	cpu_eth_init(bis);
 #endif
 

index b70bdfe..5b7c3c4 100644
@@ -689,6 +689,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 #endif
 
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x14
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x18
+
 /*
  * Dynamic MTD Partition support with mtdparts
  */

index f5c0ec8..77c1e89 100644
@@ -6,11 +6,15 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#ifdef CONFIG_VSC9953
+#include <vsc9953.h>
+#endif
 
 #include "../common/fman.h"
 

@@ -20,6 +24,11 @@ int board_eth_init(bd_t *bis)
 	struct memac_mdio_info memac_mdio_info;
 	unsigned int i;
 	int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
+
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =

@@ -81,6 +90,49 @@ int board_eth_init(bd_t *bis)
 							DEFAULT_FM_MDIO_NAME));
 	}
 
+#ifdef CONFIG_VSC9953
+	/* SerDes configured for QSGMII */
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+		for (i = 0; i < 4; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+		for (i = 4; i < 8; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+
+	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+		vsc9953_port_enable(8);
+
+	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+		/* Enable L2 On MAC2 using SCFG */
+		struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+				CONFIG_SYS_MPC85xx_SCFG;
+
+		out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+			 (0x80000000));
+		vsc9953_port_enable(9);
+	}
+#endif
+
 	cpu_eth_init(bis);
 #endif
 

index 57cdf72..c77b5d5 100644
@@ -726,6 +726,12 @@
 #define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
 #define CONFIG_SYS_RGMII2_PHY_ADDR		0x02
 
+#ifdef CONFIG_T1040RDB
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
+#endif
+
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1 at DTSEC4"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */