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ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

PATCH New Kukjin Kim 4 participants 5 messages Dec 31, 2012 – Jan 14, 2015

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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Kukjin Kim

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#0 lore raw

PATCH 1/1 ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

No need to check power on/off with pmu control to support hotplug in/out on exynos5440. And this patch enables 4 cores on exynos5440.

Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c |   37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)
arch/arm/mach-exynos/platsmp.c +22 -15
index c5c840e..495a501 100644
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
 {
 	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
 		return S5P_INFORM5;
+	else if (soc_is_exynos5440())
+		return (S5P_VA_CHIPID + 0x560);
 	return S5P_VA_SYSRAM;
 }
 

@@ -116,27 +118,30 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
 	 */
 	write_pen_release(phys_cpu);
 
-	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-			     S5P_ARM_CORE1_CONFIGURATION);
+	if (!soc_is_exynos5440()) {
+		if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+			__raw_writel(S5P_CORE_LOCAL_PWR_EN,
+				     S5P_ARM_CORE1_CONFIGURATION);
 
-		timeout = 10;
+			timeout = 10;
 
-		/* wait max 10 ms until cpu1 is on */
-		while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-			if (timeout-- == 0)
-				break;
+			/* wait max 10 ms until cpu1 is on */
+			while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+				& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+				if (timeout-- == 0)
+					break;
 
-			mdelay(1);
-		}
+				mdelay(1);
+			}
 
-		if (timeout == 0) {
-			printk(KERN_ERR "cpu1 power enable failed");
-			spin_unlock(&boot_lock);
-			return -ETIMEDOUT;
+			if (timeout == 0) {
+				printk(KERN_ERR "cpu1 power enable failed");
+				spin_unlock(&boot_lock);
+				return -ETIMEDOUT;
+			}
 		}
 	}
+
 	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,

@@ -178,6 +183,8 @@ static void __init exynos_smp_init_cpus(void)
 
 	if (soc_is_exynos5250())
 		ncores = 2;
+	else if (soc_is_exynos5440())
+		ncores = 4;
 	else
 		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
Signature · 1 line
1.7.10.4
#1 lore raw

PATCH 1/1 ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

Hi,

Quoted 22 lines · Kukjin Kim

No need to check power on/off with pmu control to support hotplug in/out on exynos5440. And this patch enables 4 cores on exynos5440.

Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c |   37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)
arch/arm/mach-exynos/platsmp.c +2 -0
index c5c840e..495a501 100644
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
 {
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
                return S5P_INFORM5;
+       else if (soc_is_exynos5440())
+               return (S5P_VA_CHIPID + 0x560);
        return S5P_VA_SYSRAM;
 }

arch/arm/mach-exynos/platsmp.c static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct · line 124

Quoted 10 lines
arch/arm/mach-exynos/platsmp.c +4 -3
@@ -116,27 +118,30 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
         */
        write_pen_release(phys_cpu);
 
-       if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-               __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                            S5P_ARM_CORE1_CONFIGURATION);
+       if (!soc_is_exynos5440()) {
+               if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+                       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                                    S5P_ARM_CORE1_CONFIGURATION);

It seems better to create a helper function here instead and calling that, instead of switching to a conditional open-coded block to this function.

arch/arm/mach-exynos/platsmp.c static void __init exynos_smp_init_cpus(void) · line 187

Quoted 6 lines
arch/arm/mach-exynos/platsmp.c +2 -0
@@ -178,6 +183,8 @@ static void __init exynos_smp_init_cpus(void)
 
        if (soc_is_exynos5250())
                ncores = 2;
+       else if (soc_is_exynos5440())
+               ncores = 4;

In the future it would make sense to get the core count from the device tree instead.

-Olof

author
#2 lore raw

PATCH 1/1 ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

Quoted 3 lines · Olof Johansson

Hi,

Hi,

[...]

Quoted 4 lines

It seems better to create a helper function here instead and calling that, instead of switching to a conditional open-coded block to this function.

Yes, sounds good. I will.

Quoted 10 lines

arch/arm/mach-exynos/platsmp.c static void __init exynos_smp_init_cpus(void) · line 187

Quoted 6 lines
arch/arm/mach-exynos/platsmp.c +2 -0
@@ -178,6 +183,8 @@ static void __init exynos_smp_init_cpus(void)
 
        if (soc_is_exynos5250())
                ncores = 2;
+       else if (soc_is_exynos5440())
+               ncores = 4;

In the future it would make sense to get the core count from the device tree instead.

Agreed.

Thanks.

- Kukjin

#3 lore raw

PATCH 1/1 ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

In reply to Kukjin Kim

Hi Kukjin,

Quoted 2 lines · Kukjin Kim

No need to check power on/off with pmu control to support hotplug in/out on exynos5440. And this patch enables 4 cores on exynos5440.

Without this patch, oops will be triggered during kernel booting on exynos5440, so could this one be pushed out?

Thanks,
Ming Lei

Quoted 82 lines
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c |   37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)
arch/arm/mach-exynos/platsmp.c +22 -16
index c5c840e..495a501 100644
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
 {
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
                return S5P_INFORM5;
+       else if (soc_is_exynos5440())
+               return (S5P_VA_CHIPID + 0x560);
        return S5P_VA_SYSRAM;
 }
 

@@ -116,27 +118,30 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
         */
        write_pen_release(phys_cpu);
 
-       if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-               __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                            S5P_ARM_CORE1_CONFIGURATION);
+       if (!soc_is_exynos5440()) {
+               if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+                       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                                    S5P_ARM_CORE1_CONFIGURATION);
 
-               timeout = 10;
+                       timeout = 10;
 
-               /* wait max 10 ms until cpu1 is on */
-               while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-                       & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-                       if (timeout-- == 0)
-                               break;
+                       /* wait max 10 ms until cpu1 is on */
+                       while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                               & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+                               if (timeout-- == 0)
+                                       break;
 
-                       mdelay(1);
-               }
+                               mdelay(1);
+                       }
 
-               if (timeout == 0) {
-                       printk(KERN_ERR "cpu1 power enable failed");
-                       spin_unlock(&boot_lock);
-                       return -ETIMEDOUT;
+                       if (timeout == 0) {
+                               printk(KERN_ERR "cpu1 power enable failed");
+                               spin_unlock(&boot_lock);
+                               return -ETIMEDOUT;
+                       }
                }
        }
+
        /*
         * Send the secondary CPU a soft interrupt, thereby causing
         * the boot monitor to read the system wide flags register,

@@ -178,6 +183,8 @@ static void __init exynos_smp_init_cpus(void)
 
        if (soc_is_exynos5250())
                ncores = 2;
+       else if (soc_is_exynos5440())
+               ncores = 4;
        else
                ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
--

1.7.10.4

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Signature · 1 line
Ming Lei
#4 lore raw

PATCH 1/1 ARM: EXYNOS: enable 4 cores secondary cpu up for exynos5440

Quoted 2 lines · Ming Lei

Hi Kukjin,

Hi Ming Lei,

Sorry for late response.

Quoted 7 lines · Kukjin Kim
Quoted 2 lines

No need to check power on/off with pmu control to support hotplug in/out on exynos5440. And this patch enables 4 cores on exynos5440.

Without this patch, oops will be triggered during kernel booting on exynos5440, so could this one be pushed out?

Yeah, I know exynos5440 requires this at least kernel boot but something like soc_is_xxx should be updated with others in these days...so I need some time for this.

Thanks,
Kukjin

Quoted 79 lines

Thanks,
Ming Lei

Quoted 76 lines
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c |   37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)
arch/arm/mach-exynos/platsmp.c +22 -16
index c5c840e..495a501 100644
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
 {
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
                return S5P_INFORM5;
+       else if (soc_is_exynos5440())
+               return (S5P_VA_CHIPID + 0x560);
        return S5P_VA_SYSRAM;
 }
 

@@ -116,27 +118,30 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
         */
        write_pen_release(phys_cpu);
 
-       if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-               __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                            S5P_ARM_CORE1_CONFIGURATION);
+       if (!soc_is_exynos5440()) {
+               if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+                       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                                    S5P_ARM_CORE1_CONFIGURATION);
 
-               timeout = 10;
+                       timeout = 10;
 
-               /* wait max 10 ms until cpu1 is on */
-               while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-                       & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-                       if (timeout-- == 0)
-                               break;
+                       /* wait max 10 ms until cpu1 is on */
+                       while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                               & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+                               if (timeout-- == 0)
+                                       break;
 
-                       mdelay(1);
-               }
+                               mdelay(1);
+                       }
 
-               if (timeout == 0) {
-                       printk(KERN_ERR "cpu1 power enable failed");
-                       spin_unlock(&boot_lock);
-                       return -ETIMEDOUT;
+                       if (timeout == 0) {
+                               printk(KERN_ERR "cpu1 power enable failed");
+                               spin_unlock(&boot_lock);
+                               return -ETIMEDOUT;
+                       }
                }
        }
+
        /*
         * Send the secondary CPU a soft interrupt, thereby causing
         * the boot monitor to read the system wide flags register,

@@ -178,6 +183,8 @@ static void __init exynos_smp_init_cpus(void)
 
        if (soc_is_exynos5250())
                ncores = 2;
+       else if (soc_is_exynos5440())
+               ncores = 4;
        else
                ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
--

1.7.10.4