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arm: socfpga: Arria V support and fixes

PATCH New Marek Vasut 5 participants 58 messages Dec 31, 2014 – Jan 30, 2015

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Arm (32-bit) SPI
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Marek Vasut

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#0 lore raw

cover arm: socfpga: Arria V support and fixes

This series brings in a couple of minor fixes (mostly coding style and sync with rocketboards u-boot) and improvements (USB UMS and DFU support for Cyclone V SoC DK). There are also fixes for DT properties in this series to make those compatible with Linux.

This series also adds Arria V SoC DK support. By adding the Arria V support, the pieces of code which are specific to a particular CPU model are now clearly isolated by an #ifdef. These #ifdef mark code which should be easy to dissolve and migrate into DT in the next step.

While at this, the SoCFPGA platform is made dependent on having a proper Device Tree available (attached at the end of U-Boot binary). The board name is no longer hard-coded into the U-Boot binary, but is instead extracted from the DT ; this is the first step toward moving to DT altogether. At this point, no new SoCFPGA platform without DT is accepted anymore.

Note: The DT files imported in this series come from Linux 3.18
mainline.

Marek Vasut (12):
arm: socfpga: Minor coding style fix
arm: socfpga: Sync Cyclone V DK pinmux configuration
arm: socfpga: Sync Cyclone V DK PLL configuration
arm: socfpga: Add USB and UDC support for Cyclone V DK
arm: socfpga: Drop cyclone5 suffix from board file name
arm: socfpga: Add Altera Arria V DK support
dt: socfpga: Rename snps,dw-spi-mmio to snps,dw-apb-ssi
dt: socfpga: Replace num-chipselect with num-cs
dt: socfpga: Import and enable Cyclone V DK DTS
dt: socfpga: Import and enable Arria V DK DTS
arm: socfpga: Zap checkboard()
arm: socfpga: Zap board_early_init_f()

 arch/arm/Kconfig                                   |   5 +
 arch/arm/dts/Makefile                              |   5 +-
 arch/arm/dts/socfpga.dtsi                          |  10 +-
 arch/arm/dts/socfpga_arria5.dtsi                   |  34 +
 arch/arm/dts/socfpga_arria5_socdk.dts              |  74 +++
 arch/arm/dts/socfpga_cyclone5_socdk.dts            |  79 +++
 board/altera/socfpga/Kconfig                       |  16 +
 board/altera/socfpga/Makefile                      |   2 +-
 board/altera/socfpga/iocsr_config.c                | 688 +++++++++++++++++++++
 board/altera/socfpga/iocsr_config.h                |  17 +-
 board/altera/socfpga/pinmux_config.c               | 403 +++++++++---
 board/altera/socfpga/pinmux_config.h               |  14 +-
 board/altera/socfpga/pll_config.h                  |  34 +-
 .../socfpga/{socfpga_cyclone5.c => socfpga.c}      |  17 -
 configs/socfpga_arria5_defconfig                   |   5 +
 configs/socfpga_cyclone5_defconfig                 |   2 +
 drivers/spi/designware_spi.c                       |   2 +-
 include/configs/socfpga_arria5.h                   | 107 ++++
 include/configs/socfpga_common.h                   |   3 +-
 include/configs/socfpga_cyclone5.h                 |   9 +
 20 files changed, 1371 insertions(+), 155 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
 rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%)
 create mode 100644 configs/socfpga_arria5_defconfig
 create mode 100644 include/configs/socfpga_arria5.h
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Signature · 1 line
2.1.3
author
#1 lore raw

PATCH 1/12 arm: socfpga: Minor coding style fix

Replace multiple spaces with a single tab.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/iocsr_config.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
board/altera/socfpga/iocsr_config.h +4 -4
index 490f109..4a7ed46 100644
@@ -9,9 +9,9 @@
 #ifndef _PRELOADER_IOCSR_CONFIG_H_
 #define _PRELOADER_IOCSR_CONFIG_H_
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH        (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH        (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH        (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH        (16766)
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)
 
 #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
Signature · 1 line
2.1.3
#2 lore raw

PATCH 1/12 arm: socfpga: Minor coding style fix

Quoted 5 lines · Marek Vasut

Replace multiple spaces with a single tab.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>

board/altera/socfpga/iocsr_config.h line 15

Quoted 4 lines
board/altera/socfpga/iocsr_config.h +4 -0
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)

Removing ()s would be nice, too.

But this is autogenerated file, so we'd need to get altera to fix their tools...?
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#3 lore raw

PATCH 1/12 arm: socfpga: Minor coding style fix

Quoted 16 lines · Pavel Machek
Quoted 5 lines · Marek Vasut

Replace multiple spaces with a single tab.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>

board/altera/socfpga/iocsr_config.h line 15

Quoted 4 lines
board/altera/socfpga/iocsr_config.h +4 -0
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)

Removing ()s would be nice, too.

Quoted 2 lines

But this is autogenerated file, so we'd need to get altera to fix their tools...?

Hi!

No, we need to get this information into DT and zap this file altogether. While this might take a bit more time, that's the ultimate goal here.

Best regards,
Marek Vasut

#5 lore raw

PATCH 1/12 arm: socfpga: Minor coding style fix

In reply to Marek Vasut
Quoted 21 lines · Marek Vasut

Replace multiple spaces with a single tab.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/iocsr_config.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
board/altera/socfpga/iocsr_config.h +0 -0
index 490f109..4a7ed46 100644
@@ -9,9 +9,9 @@
 #ifndef _PRELOADER_IOCSR_CONFIG_H_
 #define _PRELOADER_IOCSR_CONFIG_H_

board/altera/socfpga/iocsr_config.h line 17

Quoted 10 lines
board/altera/socfpga/iocsr_config.h +4 -4
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH        (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH        (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH        (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH        (16766)
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)
 
 #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
Acked-by Dinh Nguyen <[email protected]>
author
#6 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

In reply to Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------
 board/altera/socfpga/pinmux_config.h |  14 +--
 2 files changed, 101 insertions(+), 101 deletions(-)
board/altera/socfpga/pinmux_config.c +94 -94
index 8b09005..b124768 100644
@@ -4,100 +4,100 @@
 
 /* pin mux configuration data */
 unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-	0, /* EMACIO0 - Unused */
-	2, /* EMACIO1 - USB */
-	2, /* EMACIO2 - USB */
-	2, /* EMACIO3 - USB */
-	2, /* EMACIO4 - USB */
-	2, /* EMACIO5 - USB */
-	2, /* EMACIO6 - USB */
-	2, /* EMACIO7 - USB */
-	2, /* EMACIO8 - USB */
-	0, /* EMACIO9 - Unused */
-	2, /* EMACIO10 - USB */
-	2, /* EMACIO11 - USB */
-	2, /* EMACIO12 - USB */
-	2, /* EMACIO13 - USB */
-	0, /* EMACIO14 - N/A */
-	0, /* EMACIO15 - N/A */
-	0, /* EMACIO16 - N/A */
-	0, /* EMACIO17 - N/A */
-	0, /* EMACIO18 - N/A */
-	0, /* EMACIO19 - N/A */
-	3, /* FLASHIO0 - SDMMC */
-	3, /* FLASHIO1 - SDMMC */
-	3, /* FLASHIO2 - SDMMC */
-	3, /* FLASHIO3 - SDMMC */
-	0, /* FLASHIO4 - SDMMC */
-	0, /* FLASHIO5 - SDMMC */
-	0, /* FLASHIO6 - SDMMC */
-	0, /* FLASHIO7 - SDMMC */
-	0, /* FLASHIO8 - SDMMC */
-	3, /* FLASHIO9 - SDMMC */
-	3, /* FLASHIO10 - SDMMC */
-	3, /* FLASHIO11 - SDMMC */
-	3, /* GENERALIO0 - TRACE */
-	3, /* GENERALIO1 - TRACE */
-	3, /* GENERALIO2 - TRACE */
-	3, /* GENERALIO3 - TRACE  */
-	3, /* GENERALIO4 - TRACE  */
-	3, /* GENERALIO5 - TRACE  */
-	3, /* GENERALIO6 - TRACE  */
-	3, /* GENERALIO7 - TRACE  */
-	3, /* GENERALIO8 - TRACE  */
-	3, /* GENERALIO9 - SPIM0 */
-	3, /* GENERALIO10 - SPIM0 */
-	3, /* GENERALIO11 - SPIM0 */
-	3, /* GENERALIO12 - SPIM0 */
-	2, /* GENERALIO13 - CAN0 */
-	2, /* GENERALIO14 - CAN0 */
-	3, /* GENERALIO15 - I2C0 */
-	3, /* GENERALIO16 - I2C0 */
-	2, /* GENERALIO17 - UART0 */
-	2, /* GENERALIO18 - UART0 */
-	0, /* GENERALIO19 - N/A */
-	0, /* GENERALIO20 - N/A */
-	0, /* GENERALIO21 - N/A */
-	0, /* GENERALIO22 - N/A */
-	0, /* GENERALIO23 - N/A */
-	0, /* GENERALIO24 - N/A */
-	0, /* GENERALIO25 - N/A */
-	0, /* GENERALIO26 - N/A */
-	0, /* GENERALIO27 - N/A */
-	0, /* GENERALIO28 - N/A */
-	0, /* GENERALIO29 - N/A */
-	0, /* GENERALIO30 - N/A */
-	0, /* GENERALIO31 - N/A */
-	2, /* MIXED1IO0 - EMAC */
-	2, /* MIXED1IO1 - EMAC */
-	2, /* MIXED1IO2 - EMAC */
-	2, /* MIXED1IO3 - EMAC */
-	2, /* MIXED1IO4 - EMAC */
-	2, /* MIXED1IO5 - EMAC */
-	2, /* MIXED1IO6 - EMAC */
-	2, /* MIXED1IO7 - EMAC */
-	2, /* MIXED1IO8 - EMAC */
-	2, /* MIXED1IO9 - EMAC */
-	2, /* MIXED1IO10 - EMAC */
-	2, /* MIXED1IO11 - EMAC */
-	2, /* MIXED1IO12 - EMAC */
-	2, /* MIXED1IO13 - EMAC */
-	0, /* MIXED1IO14 - Unused */
-	3, /* MIXED1IO15 - QSPI */
-	3, /* MIXED1IO16 - QSPI */
-	3, /* MIXED1IO17 - QSPI */
-	3, /* MIXED1IO18 - QSPI */
-	3, /* MIXED1IO19 - QSPI */
-	3, /* MIXED1IO20 - QSPI */
-	0, /* MIXED1IO21 - GPIO */
-	0, /* MIXED2IO0 - N/A */
-	0, /* MIXED2IO1 - N/A */
-	0, /* MIXED2IO2 - N/A */
-	0, /* MIXED2IO3 - N/A */
-	0, /* MIXED2IO4 - N/A */
-	0, /* MIXED2IO5 - N/A */
-	0, /* MIXED2IO6 - N/A */
-	0, /* MIXED2IO7 - N/A */
+	3, /* EMACIO0 */
+	3, /* EMACIO1 */
+	3, /* EMACIO2 */
+	3, /* EMACIO3 */
+	3, /* EMACIO4 */
+	3, /* EMACIO5 */
+	3, /* EMACIO6 */
+	3, /* EMACIO7 */
+	3, /* EMACIO8 */
+	3, /* EMACIO9 */
+	3, /* EMACIO10 */
+	3, /* EMACIO11 */
+	3, /* EMACIO12 */
+	3, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	3, /* FLASHIO4 */
+	3, /* FLASHIO5 */
+	3, /* FLASHIO6 */
+	3, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	0, /* GENERALIO3 */
+	0, /* GENERALIO4 */
+	1, /* GENERALIO5 */
+	1, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	2, /* GENERALIO13 */
+	2, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	0, /* MIXED1IO0 */
+	1, /* MIXED1IO1 */
+	1, /* MIXED1IO2 */
+	1, /* MIXED1IO3 */
+	1, /* MIXED1IO4 */
+	0, /* MIXED1IO5 */
+	0, /* MIXED1IO6 */
+	0, /* MIXED1IO7 */
+	1, /* MIXED1IO8 */
+	1, /* MIXED1IO9 */
+	1, /* MIXED1IO10 */
+	1, /* MIXED1IO11 */
+	0, /* MIXED1IO12 */
+	0, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	1, /* MIXED1IO15 */
+	1, /* MIXED1IO16 */
+	1, /* MIXED1IO17 */
+	1, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
 	0, /* GPLINMUX48 */
 	0, /* GPLINMUX49 */
 	0, /* GPLINMUX50 */
board/altera/socfpga/pinmux_config.h +7 -7
index f278f2b..21fabb0 100644
@@ -7,21 +7,21 @@
  * State of enabling for which IP connected out through the muxing.
  * Value 1 mean the IP connection is muxed out
  */
-#define CONFIG_HPS_EMAC0		(0)
-#define CONFIG_HPS_EMAC1		(1)
+#define CONFIG_HPS_EMAC0		(1)
+#define CONFIG_HPS_EMAC1		(0)
 #define CONFIG_HPS_USB0			(0)
 #define CONFIG_HPS_USB1			(1)
 #define CONFIG_HPS_NAND			(0)
 #define CONFIG_HPS_SDMMC		(1)
-#define CONFIG_HPS_QSPI			(1)
+#define CONFIG_HPS_QSPI			(0)
 #define CONFIG_HPS_UART0		(1)
 #define CONFIG_HPS_UART1		(0)
-#define CONFIG_HPS_TRACE		(1)
+#define CONFIG_HPS_TRACE		(0)
 #define CONFIG_HPS_I2C0			(1)
 #define CONFIG_HPS_I2C1			(0)
 #define CONFIG_HPS_I2C2			(0)
 #define CONFIG_HPS_I2C3			(0)
-#define CONFIG_HPS_SPIM0		(1)
+#define CONFIG_HPS_SPIM0		(0)
 #define CONFIG_HPS_SPIM1		(0)
 #define CONFIG_HPS_SPIS0		(0)
 #define CONFIG_HPS_SPIS1		(0)

@@ -29,10 +29,10 @@
 #define CONFIG_HPS_CAN1			(0)
 
 /* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH	(4)
+#define CONFIG_HPS_SDMMC_BUSWIDTH	(8)
 
 /* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0		(1)
+#define CONFIG_HPS_QSPI_CS0		(0)
 #define CONFIG_HPS_QSPI_CS1		(0)
 #define CONFIG_HPS_QSPI_CS2		(0)
 #define CONFIG_HPS_QSPI_CS3		(0)
Signature · 1 line
2.1.3
#7 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

Quoted 9 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>

Will this break the other socfpga targets? Because tables are completely different...
Pavel

Quoted 248 lines
---
 board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------
 board/altera/socfpga/pinmux_config.h |  14 +--
 2 files changed, 101 insertions(+), 101 deletions(-)
board/altera/socfpga/pinmux_config.c +94 -94
index 8b09005..b124768 100644
@@ -4,100 +4,100 @@
 
 /* pin mux configuration data */
 unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-	0, /* EMACIO0 - Unused */
-	2, /* EMACIO1 - USB */
-	2, /* EMACIO2 - USB */
-	2, /* EMACIO3 - USB */
-	2, /* EMACIO4 - USB */
-	2, /* EMACIO5 - USB */
-	2, /* EMACIO6 - USB */
-	2, /* EMACIO7 - USB */
-	2, /* EMACIO8 - USB */
-	0, /* EMACIO9 - Unused */
-	2, /* EMACIO10 - USB */
-	2, /* EMACIO11 - USB */
-	2, /* EMACIO12 - USB */
-	2, /* EMACIO13 - USB */
-	0, /* EMACIO14 - N/A */
-	0, /* EMACIO15 - N/A */
-	0, /* EMACIO16 - N/A */
-	0, /* EMACIO17 - N/A */
-	0, /* EMACIO18 - N/A */
-	0, /* EMACIO19 - N/A */
-	3, /* FLASHIO0 - SDMMC */
-	3, /* FLASHIO1 - SDMMC */
-	3, /* FLASHIO2 - SDMMC */
-	3, /* FLASHIO3 - SDMMC */
-	0, /* FLASHIO4 - SDMMC */
-	0, /* FLASHIO5 - SDMMC */
-	0, /* FLASHIO6 - SDMMC */
-	0, /* FLASHIO7 - SDMMC */
-	0, /* FLASHIO8 - SDMMC */
-	3, /* FLASHIO9 - SDMMC */
-	3, /* FLASHIO10 - SDMMC */
-	3, /* FLASHIO11 - SDMMC */
-	3, /* GENERALIO0 - TRACE */
-	3, /* GENERALIO1 - TRACE */
-	3, /* GENERALIO2 - TRACE */
-	3, /* GENERALIO3 - TRACE  */
-	3, /* GENERALIO4 - TRACE  */
-	3, /* GENERALIO5 - TRACE  */
-	3, /* GENERALIO6 - TRACE  */
-	3, /* GENERALIO7 - TRACE  */
-	3, /* GENERALIO8 - TRACE  */
-	3, /* GENERALIO9 - SPIM0 */
-	3, /* GENERALIO10 - SPIM0 */
-	3, /* GENERALIO11 - SPIM0 */
-	3, /* GENERALIO12 - SPIM0 */
-	2, /* GENERALIO13 - CAN0 */
-	2, /* GENERALIO14 - CAN0 */
-	3, /* GENERALIO15 - I2C0 */
-	3, /* GENERALIO16 - I2C0 */
-	2, /* GENERALIO17 - UART0 */
-	2, /* GENERALIO18 - UART0 */
-	0, /* GENERALIO19 - N/A */
-	0, /* GENERALIO20 - N/A */
-	0, /* GENERALIO21 - N/A */
-	0, /* GENERALIO22 - N/A */
-	0, /* GENERALIO23 - N/A */
-	0, /* GENERALIO24 - N/A */
-	0, /* GENERALIO25 - N/A */
-	0, /* GENERALIO26 - N/A */
-	0, /* GENERALIO27 - N/A */
-	0, /* GENERALIO28 - N/A */
-	0, /* GENERALIO29 - N/A */
-	0, /* GENERALIO30 - N/A */
-	0, /* GENERALIO31 - N/A */
-	2, /* MIXED1IO0 - EMAC */
-	2, /* MIXED1IO1 - EMAC */
-	2, /* MIXED1IO2 - EMAC */
-	2, /* MIXED1IO3 - EMAC */
-	2, /* MIXED1IO4 - EMAC */
-	2, /* MIXED1IO5 - EMAC */
-	2, /* MIXED1IO6 - EMAC */
-	2, /* MIXED1IO7 - EMAC */
-	2, /* MIXED1IO8 - EMAC */
-	2, /* MIXED1IO9 - EMAC */
-	2, /* MIXED1IO10 - EMAC */
-	2, /* MIXED1IO11 - EMAC */
-	2, /* MIXED1IO12 - EMAC */
-	2, /* MIXED1IO13 - EMAC */
-	0, /* MIXED1IO14 - Unused */
-	3, /* MIXED1IO15 - QSPI */
-	3, /* MIXED1IO16 - QSPI */
-	3, /* MIXED1IO17 - QSPI */
-	3, /* MIXED1IO18 - QSPI */
-	3, /* MIXED1IO19 - QSPI */
-	3, /* MIXED1IO20 - QSPI */
-	0, /* MIXED1IO21 - GPIO */
-	0, /* MIXED2IO0 - N/A */
-	0, /* MIXED2IO1 - N/A */
-	0, /* MIXED2IO2 - N/A */
-	0, /* MIXED2IO3 - N/A */
-	0, /* MIXED2IO4 - N/A */
-	0, /* MIXED2IO5 - N/A */
-	0, /* MIXED2IO6 - N/A */
-	0, /* MIXED2IO7 - N/A */
+	3, /* EMACIO0 */
+	3, /* EMACIO1 */
+	3, /* EMACIO2 */
+	3, /* EMACIO3 */
+	3, /* EMACIO4 */
+	3, /* EMACIO5 */
+	3, /* EMACIO6 */
+	3, /* EMACIO7 */
+	3, /* EMACIO8 */
+	3, /* EMACIO9 */
+	3, /* EMACIO10 */
+	3, /* EMACIO11 */
+	3, /* EMACIO12 */
+	3, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	3, /* FLASHIO4 */
+	3, /* FLASHIO5 */
+	3, /* FLASHIO6 */
+	3, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	0, /* GENERALIO3 */
+	0, /* GENERALIO4 */
+	1, /* GENERALIO5 */
+	1, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	2, /* GENERALIO13 */
+	2, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	0, /* MIXED1IO0 */
+	1, /* MIXED1IO1 */
+	1, /* MIXED1IO2 */
+	1, /* MIXED1IO3 */
+	1, /* MIXED1IO4 */
+	0, /* MIXED1IO5 */
+	0, /* MIXED1IO6 */
+	0, /* MIXED1IO7 */
+	1, /* MIXED1IO8 */
+	1, /* MIXED1IO9 */
+	1, /* MIXED1IO10 */
+	1, /* MIXED1IO11 */
+	0, /* MIXED1IO12 */
+	0, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	1, /* MIXED1IO15 */
+	1, /* MIXED1IO16 */
+	1, /* MIXED1IO17 */
+	1, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
 	0, /* GPLINMUX48 */
 	0, /* GPLINMUX49 */
 	0, /* GPLINMUX50 */
board/altera/socfpga/pinmux_config.h +7 -7
index f278f2b..21fabb0 100644
@@ -7,21 +7,21 @@
  * State of enabling for which IP connected out through the muxing.
  * Value 1 mean the IP connection is muxed out
  */
-#define CONFIG_HPS_EMAC0		(0)
-#define CONFIG_HPS_EMAC1		(1)
+#define CONFIG_HPS_EMAC0		(1)
+#define CONFIG_HPS_EMAC1		(0)
 #define CONFIG_HPS_USB0			(0)
 #define CONFIG_HPS_USB1			(1)
 #define CONFIG_HPS_NAND			(0)
 #define CONFIG_HPS_SDMMC		(1)
-#define CONFIG_HPS_QSPI			(1)
+#define CONFIG_HPS_QSPI			(0)
 #define CONFIG_HPS_UART0		(1)
 #define CONFIG_HPS_UART1		(0)
-#define CONFIG_HPS_TRACE		(1)
+#define CONFIG_HPS_TRACE		(0)
 #define CONFIG_HPS_I2C0			(1)
 #define CONFIG_HPS_I2C1			(0)
 #define CONFIG_HPS_I2C2			(0)
 #define CONFIG_HPS_I2C3			(0)
-#define CONFIG_HPS_SPIM0		(1)
+#define CONFIG_HPS_SPIM0		(0)
 #define CONFIG_HPS_SPIM1		(0)
 #define CONFIG_HPS_SPIS0		(0)
 #define CONFIG_HPS_SPIS1		(0)

@@ -29,10 +29,10 @@
 #define CONFIG_HPS_CAN1			(0)
 
 /* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH	(4)
+#define CONFIG_HPS_SDMMC_BUSWIDTH	(8)
 
 /* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0		(1)
+#define CONFIG_HPS_QSPI_CS0		(0)
 #define CONFIG_HPS_QSPI_CS1		(0)
 #define CONFIG_HPS_QSPI_CS2		(0)
 #define CONFIG_HPS_QSPI_CS3		(0)
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#8 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

Quoted 11 lines · Pavel Machek
Quoted 9 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 2 lines

Will this break the other socfpga targets? Because tables are completely different...

Mainline only supports socdk and socrates, which do work with this patch. In case this did break some out-of-mainline boards, that cannot really be helped at this point.

Still, this is only used in (already broken) SPL, so there's really nothing much to be worried about there. The ultimate goal is to use pinmux from the DT and zap this file.

Best regards,
Marek Vasut

#9 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

In reply to Marek Vasut
Quoted 9 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>

This is all for SPL only, right? Not sure if we should change these defines / values now even though its not really used in mainline. But it doesn't hurt. So:

Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

author
#10 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

Quoted 4 lines · Stefan Roese
Quoted 3 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Quoted 8 lines
Quoted 6 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>

This is all for SPL only, right?

Yes.

Quoted 3 lines

Not sure if we should change these
defines / values now even though its not really used in mainline. But it doesn't hurt. So:

It doesn't hurt keeping closer to RocketBoards for the time being I guess.

Quoted 1 line
Reviewed-by Stefan Roese <[email protected]>

Thanks!

Best regards,
Marek Vasut

#11 lore raw

PATCH 2/12 arm: socfpga: Sync Cyclone V DK pinmux configuration

In reply to Marek Vasut
Quoted 19 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------
 board/altera/socfpga/pinmux_config.h |  14 +--
 2 files changed, 101 insertions(+), 101 deletions(-)
board/altera/socfpga/pinmux_config.c +0 -0
index 8b09005..b124768 100644

board/altera/socfpga/pinmux_config.c line 5

Quoted 2 lines
board/altera/socfpga/pinmux_config.c +0 -0
@@ -4,100 +4,100 @@
 
 /* pin mux configuration data */
Acked-by Dinh Nguyen <[email protected]>
author
#12 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

In reply to Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/pll_config.h | 34 +++++++++++-----------------------
 1 file changed, 11 insertions(+), 23 deletions(-)
board/altera/socfpga/pll_config.h +11 -23
index f0f59a9..8130fa4 100644
@@ -16,9 +16,9 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(15)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)

@@ -36,7 +36,7 @@
 
 /* Peripheral PLL */
 #define CONFIG_HPS_PERPLLGRP_VCO_DENOM			(1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(79)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(39)
 /*
  * To tell where is the VCOs source:
  * 0 = EOSC1

@@ -45,13 +45,13 @@
  */
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC			(0)
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		(3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(1)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(511)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(511)
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT	(4)
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		(4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(511)
 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK			(0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(4)
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		(1)
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		(1)
 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		(6249)

@@ -66,15 +66,8 @@
 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI			(1)
 
 /* SDRAM PLL */
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
- * This if..else... is not required if generated by tools */
 #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(127)
-#else
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(31)
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(79)
 
 /*
  * To tell where is the VCOs source:

@@ -94,17 +87,12 @@
 
 /* Info for driver */
 #define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ			0
+#define CONFIG_HPS_CLK_OSC2_HZ			(25000000)
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ		0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ		0
 #define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
 #define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CONFIG_HPS_CLK_SDRVCO_HZ		(1066000000)
-#else
-#define CONFIG_HPS_CLK_SDRVCO_HZ		(800000000)
-#endif
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(666666666)
 #define CONFIG_HPS_CLK_EMAC0_HZ			(250000000)
 #define CONFIG_HPS_CLK_EMAC1_HZ			(250000000)
 #define CONFIG_HPS_CLK_USBCLK_HZ		(200000000)
Signature · 1 line
2.1.3
#13 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

Quoted 5 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.

Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#14 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

Quoted 10 lines · Pavel Machek
Quoted 6 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at

which point this will likely need further rework.

Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)

I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?

Best regards,
Marek Vasut

#15 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

Quoted 7 lines · Marek Vasut
Quoted 6 lines · Pavel Machek
Quoted 5 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

which point this will likely need further rework.

Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)

I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?

No problem for me, but it is strange to update files that are not used. Does it solve any problem for you?

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#16 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

Quoted 10 lines · Pavel Machek
Quoted 9 lines · Marek Vasut
Quoted 8 lines · Pavel Machek
Quoted 6 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at

which point this will likely need further rework.

Quoted 8 lines
Quoted 5 lines
Quoted 2 lines

Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)

I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?

No problem for me, but it is strange to update files that are not used. Does it solve any problem for you?

No, it's just less divergence between the codebases, which I believe is always an improvement.

Best regards,
Marek Vasut

#17 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

In reply to Marek Vasut
Quoted 6 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.

Quoted 6 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>

Same comment as on the patch before. Not sure if we should change these defines / values now even though its not really used in mainline. But it doesn't hurt. So:

Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#18 lore raw

PATCH 3/12 arm: socfpga: Sync Cyclone V DK PLL configuration

In reply to Marek Vasut
Quoted 12 lines · Marek Vasut

Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 4 lines
---
 board/altera/socfpga/pll_config.h | 34 +++++++++++-----------------------
 1 file changed, 11 insertions(+), 23 deletions(-)
Acked-by Dinh Nguyen <[email protected]>
author
#19 lore raw

PATCH 4/12 arm: socfpga: Add USB and UDC support for Cyclone V DK

In reply to Marek Vasut

Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 include/configs/socfpga_cyclone5.h | 9 +++++++++
 1 file changed, 9 insertions(+)
include/configs/socfpga_cyclone5.h +9 -0
index c3d958c..676144a 100644
@@ -21,6 +21,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE

@@ -33,6 +34,8 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
 
 #define CONFIG_REGEX			/* Enable regular expression support */
 

@@ -66,6 +69,12 @@
 
 #endif
 
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER      "Altera"
+
 /* Extra Environment */
 #define CONFIG_HOSTNAME		socfpga_cyclone5
Signature · 1 line
2.1.3
#20 lore raw

PATCH 4/12 arm: socfpga: Add USB and UDC support for Cyclone V DK

Quoted 10 lines · Marek Vasut

Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#21 lore raw

PATCH 4/12 arm: socfpga: Add USB and UDC support for Cyclone V DK

In reply to Marek Vasut
Quoted 7 lines · Marek Vasut

Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.

Quoted 6 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#22 lore raw

PATCH 4/12 arm: socfpga: Add USB and UDC support for Cyclone V DK

In reply to Marek Vasut
Quoted 13 lines · Marek Vasut

Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 4 lines
---
 include/configs/socfpga_cyclone5.h | 9 +++++++++
 1 file changed, 9 insertions(+)
Acked-by Dinh Nguyen <[email protected]>
author
#23 lore raw

PATCH 5/12 arm: socfpga: Drop cyclone5 suffix from board file name

In reply to Marek Vasut

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/Makefile                          | 2 +-
 board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (100%)
board/altera/socfpga/Makefile +1 -1
index 44baa00..c867f73 100644
@@ -6,5 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= socfpga_cyclone5.o
+obj-y	:= socfpga.o
 obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
board/altera/socfpga/socfpga.c renamed from board/altera/socfpga/socfpga_cyclone5.c +0 -0
similarity index 100%
rename from board/altera/socfpga/socfpga_cyclone5.c
rename to board/altera/socfpga/socfpga.c
Signature · 1 line
2.1.3
#24 lore raw

PATCH 5/12 arm: socfpga: Drop cyclone5 suffix from board file name

Quoted 6 lines · Marek Vasut

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#25 lore raw

PATCH 5/12 arm: socfpga: Drop cyclone5 suffix from board file name

In reply to Marek Vasut
Quoted 9 lines · Marek Vasut

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#26 lore raw

PATCH 5/12 arm: socfpga: Drop cyclone5 suffix from board file name

In reply to Marek Vasut

board/altera/socfpga/socfpga.c

Quoted 31 lines · Marek Vasut

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/Makefile                          | 2 +-
 board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (100%)
board/altera/socfpga/Makefile +1 -1
index 44baa00..c867f73 100644
@@ -6,5 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= socfpga_cyclone5.o
+obj-y	:= socfpga.o
 obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
board/altera/socfpga/socfpga.c renamed from board/altera/socfpga/socfpga_cyclone5.c +0 -0
similarity index 100%
rename from board/altera/socfpga/socfpga_cyclone5.c
rename to board/altera/socfpga/socfpga.c
Acked-by Dinh Nguyen <[email protected]>
author
#27 lore raw

PATCH 6/12 arm: socfpga: Add Altera Arria V DK support

In reply to Marek Vasut

Add support for the Altera Arria V development kit.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/Kconfig                     |   5 +
 board/altera/socfpga/Kconfig         |  16 +
 board/altera/socfpga/iocsr_config.c  | 688 +++++++++++++++++++++++++++++++++++
 board/altera/socfpga/iocsr_config.h  |   9 +
 board/altera/socfpga/pinmux_config.c | 215 +++++++++++
 board/altera/socfpga/socfpga.c       |   7 +
 configs/socfpga_arria5_defconfig     |   3 +
 include/configs/socfpga_arria5.h     | 107 ++++++
 8 files changed, 1050 insertions(+)
 create mode 100644 configs/socfpga_arria5_defconfig
 create mode 100644 include/configs/socfpga_arria5.h
arch/arm/Kconfig +5 -0
index 5eb1d03..0a04cca 100644
@@ -687,6 +687,11 @@ config TARGET_CM_FX6
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_SOCFPGA_ARRIA5
+	bool "Support socfpga_arria5"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_SOCFPGA_CYCLONE5
 	bool "Support socfpga_cyclone5"
 	select CPU_V7
board/altera/socfpga/Kconfig +16 -0
index fc42185..cbed8d6 100644
@@ -13,3 +13,19 @@ config SYS_CONFIG_NAME
 	default "socfpga_cyclone5"
 
 endif
+
+if TARGET_SOCFPGA_ARRIA5
+
+config SYS_BOARD
+	default "socfpga"
+
+config SYS_VENDOR
+	default "altera"
+
+config SYS_SOC
+	default "socfpga"
+
+config SYS_CONFIG_NAME
+	default "socfpga_arria5"
+
+endif
board/altera/socfpga/iocsr_config.c +688 -0

697 lines not on this page · raw message

board/altera/socfpga/iocsr_config.h +9 -0
index 4a7ed46..d1c9b0d 100644
@@ -9,9 +9,18 @@
 #ifndef _PRELOADER_IOCSR_CONFIG_H_
 #define _PRELOADER_IOCSR_CONFIG_H_
 
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
 #define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
 #define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
 #define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
 #define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(1337)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(1528)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)
+#endif
 
 #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
board/altera/socfpga/pinmux_config.c +215 -0

224 lines not on this page · raw message

board/altera/socfpga/socfpga.c +7 -0
index 459d82f..a9c330d 100644
@@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
 	puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+	puts("BOARD: Altera SoCFPGA Arria5 Board\n");
+#endif
+
 	return 0;
 }
configs/socfpga_arria5_defconfig new file +3 -0
new file mode 100644
index 0000000..f290042
@@ -0,0 +1,3 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
include/configs/socfpga_arria5.h new file +107 -0

107 lines not on this page · raw message

Signature · 1 line
2.1.3
#28 lore raw

PATCH 6/12 arm: socfpga: Add Altera Arria V DK support

Quoted 8 lines · Marek Vasut

Add support for the Altera Arria V development kit.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 6 lines
---
 arch/arm/Kconfig                     |   5 +
 board/altera/socfpga/iocsr_config.c  | 688 +++++++++++++++++++++++++++++++++++
 board/altera/socfpga/iocsr_config.h  |   9 +
 board/altera/socfpga/pinmux_config.c | 215 +++++++++++

These are normally autogenerated, how does that work?

Quoted 3 lines
 board/altera/socfpga/socfpga.c       |   7 +
 configs/socfpga_arria5_defconfig     |   3 +
 include/configs/socfpga_arria5.h     | 107 ++++++

These look better. Can more defines be moved to common socfpga.h.

Thanks,
Pavel

Quoted 113 lines
include/configs/socfpga_arria5.h new file +107 -0
new file mode 100644
index 0000000..668a91e
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_REGEX			/* Enable regular expression support */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
+
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER      "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME		socfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_ARRIA5_H__ */
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#29 lore raw

PATCH 6/12 arm: socfpga: Add Altera Arria V DK support

Quoted 11 lines · Pavel Machek
Quoted 10 lines · Marek Vasut

Add support for the Altera Arria V development kit.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>

---

Quoted 8 lines
Quoted 6 lines
 arch/arm/Kconfig                     |   5 +
 board/altera/socfpga/iocsr_config.c  | 688
 +++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h
  |   9 +
 board/altera/socfpga/pinmux_config.c | 215 +++++++++++

These are normally autogenerated, how does that work?

I just pulled the default from rocketboards source.

Quoted 5 lines
Quoted 3 lines
 board/altera/socfpga/socfpga.c       |   7 +
 configs/socfpga_arria5_defconfig     |   3 +
 include/configs/socfpga_arria5.h     | 107 ++++++

These look better. Can more defines be moved to common socfpga.h.

I'd be much happier to move toward DT. The pinmux should be a particularly low hanging fruit.

The defines here are added really only so the build would not complain until we move to DT. Basic sketch of that is already further down in the series, though for now that's U-Boot (not SPL) only.

Best regards,
Marek Vasut

#30 lore raw

PATCH 6/12 arm: socfpga: Add Altera Arria V DK support

In reply to Marek Vasut
Quoted 21 lines · Marek Vasut

Add support for the Altera Arria V development kit.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/Kconfig                     |   5 +
 board/altera/socfpga/Kconfig         |  16 +
 board/altera/socfpga/iocsr_config.c  | 688 +++++++++++++++++++++++++++++++++++
 board/altera/socfpga/iocsr_config.h  |   9 +
 board/altera/socfpga/pinmux_config.c | 215 +++++++++++
 board/altera/socfpga/socfpga.c       |   7 +
 configs/socfpga_arria5_defconfig     |   3 +
 include/configs/socfpga_arria5.h     | 107 ++++++
 8 files changed, 1050 insertions(+)
 create mode 100644 configs/socfpga_arria5_defconfig
 create mode 100644 include/configs/socfpga_arria5.h

<snip>

Quoted 8 lines
board/altera/socfpga/socfpga.c +0 -0
index 459d82f..a9c330d 100644
@@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int checkboard(void)
 {

board/altera/socfpga/socfpga.c DECLARE_GLOBAL_DATA_PTR; · line 35

Quoted 10 lines
board/altera/socfpga/socfpga.c +7 -0
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
 	puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+	puts("BOARD: Altera SoCFPGA Arria5 Board\n");
+#endif
+
 	return 0;
 }

Do you need this change here only to get zapped in patch 11/12. No objections really, just an observation.

Acked-by Dinh Nguyen <[email protected]>
author
#31 lore raw

PATCH 6/12 arm: socfpga: Add Altera Arria V DK support

Quoted 1 line · Dinh Nguyen

On 12/31/14 1:14 PM, Marek Vasut wrote:

Hi!

Quoted 22 lines
Quoted 22 lines
(quoted diff) +0 -0

b/board/altera/socfpga/socfpga.c index 459d82f..a9c330d 100644

board/altera/socfpga/socfpga.c +7 -0
@@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
  */
 
 int checkboard(void)
 {
 
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
 
 	puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
 
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+	puts("BOARD: Altera SoCFPGA Arria5 Board\n");
+#endif
+
Quoted 6 lines
Quoted 3 lines

return 0;

}

Do you need this change here only to get zapped in patch 11/12. No objections really, just an observation.

You're right, I re-ordered the patches to cater for this. Thanks!

Best regards,
Marek Vasut

author
#32 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

In reply to Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/dts/socfpga.dtsi    | 4 ++--
 drivers/spi/designware_spi.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/dts/socfpga.dtsi +2 -2
index 969e5ad..93d3776 100644
@@ -644,7 +644,7 @@
 		};
 
 		spi0: spi at fff00000 {
-			compatible = "snps,dw-spi-mmio";
+			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff00000 0x1000>;

@@ -658,7 +658,7 @@
 		};
 
 		spi1: spi at fff01000 {
-			compatible = "snps,dw-spi-mmio";
+			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff01000 0x1000>;
drivers/spi/designware_spi.c +1 -1
index 98c9f03..a42c0af 100644
@@ -409,7 +409,7 @@ static const struct dm_spi_ops dw_spi_ops = {
 };
 
 static const struct udevice_id dw_spi_ids[] = {
-	{ .compatible = "snps,dw-spi-mmio" },
+	{ .compatible = "snps,dw-apb-ssi" },
 	{ }
 };
Signature · 1 line
2.1.3
#33 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Quoted 9 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#34 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

In reply to Marek Vasut
Quoted 6 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#35 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Quoted 10 lines · Pavel Machek
Quoted 6 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Quoted 7 lines

--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Applied to u-boot-spi/master

thanks!

Signature · 1 line
Jagan.
author
#36 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Quoted 20 lines · Jagan Teki
Quoted 10 lines · Pavel Machek
Quoted 6 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Quoted 8 lines

--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 1 line

Applied to u-boot-spi/master

Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .

Thanks!

Best regards,
Marek Vasut

#37 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Quoted 21 lines · Marek Vasut
Quoted 20 lines · Jagan Teki
Quoted 18 lines · Pavel Machek
Quoted 6 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>

--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 4 lines
Quoted 1 line

Applied to u-boot-spi/master

Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .

Yes - pls confirm this is 08/12
"[PATCH 08/12] dt: socfpga: Replace num-chipselect with num-cs"

thanks!

Signature · 1 line
Jagan.
author
#38 lore raw

PATCH 7/12 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Quoted 23 lines · Jagan Teki
Quoted 22 lines · Marek Vasut
Quoted 21 lines · Jagan Teki
Quoted 19 lines · Pavel Machek
Quoted 7 lines · Marek Vasut

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>

--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

Applied to u-boot-spi/master

Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .

Yes - pls confirm this is 08/12
"[PATCH 08/12] dt: socfpga: Replace num-chipselect with num-cs"

Yes it is ^^^^^ ;-)

Please make sure these two land in current release then, since we don't want to introduce incompatible DT props. Thanks!

Best regards,
Marek Vasut

author
#39 lore raw

PATCH 8/12 dt: socfpga: Replace num-chipselect with num-cs

In reply to Marek Vasut

This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/dts/socfpga.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm/dts/socfpga.dtsi +3 -3
index 93d3776..bf791c5 100644
@@ -637,7 +637,7 @@
 			interrupts = <0 151 4>;
 			clocks = <&qspi_clk>;
 			ext-decoder = <0>;  /* external decoder */
-			num-chipselect = <4>;
+			num-cs = <4>;
 			fifo-depth = <128>;
 			bus-num = <2>;
 			status = "disabled";

@@ -649,7 +649,7 @@
 			#size-cells = <0>;
 			reg = <0xfff00000 0x1000>;
 			interrupts = <0 154 4>;
-			num-chipselect = <4>;
+			num-cs = <4>;
 			bus-num = <0>;
 			tx-dma-channel = <&pdma 16>;
 			rx-dma-channel = <&pdma 17>;

@@ -663,7 +663,7 @@
 			#size-cells = <0>;
 			reg = <0xfff01000 0x1000>;
 			interrupts = <0 156 4>;
-			num-chipselect = <4>;
+			num-cs = <4>;
 			bus-num = <1>;
 			tx-dma-channel = <&pdma 20>;
 			rx-dma-channel = <&pdma 21>;
Signature · 1 line
2.1.3
#40 lore raw

PATCH 8/12 dt: socfpga: Replace num-chipselect with num-cs

Quoted 5 lines · Marek Vasut

This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#41 lore raw

PATCH 8/12 dt: socfpga: Replace num-chipselect with num-cs

Quoted 11 lines · Pavel Machek
Quoted 5 lines · Marek Vasut

This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>

--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Applied to u-boot-spi/master

thanks!

Signature · 1 line
Jagan.
author
#42 lore raw

PATCH 9/12 dt: socfpga: Import and enable Cyclone V DK DTS

In reply to Marek Vasut

Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/dts/Makefile                   |  4 +-
 arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 +++++++++++++++++++++++++++++++++
 configs/socfpga_cyclone5_defconfig      |  2 +
 3 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
arch/arm/dts/Makefile +3 -1
index e6a495c..c851d65 100644
@@ -48,7 +48,9 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_SOCFPGA) +=				\
+	socfpga_cyclone5_socdk.dtb			\
+	socfpga_cyclone5_socrates.dtb
 
 targets += $(dtb-y)
arch/arm/dts/socfpga_cyclone5_socdk.dts new file +79 -0

79 lines not on this page · raw message

configs/socfpga_cyclone5_defconfig +2 -0
index 4b2ede4..2d3dd47 100644
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
Signature · 1 line
2.1.3
#43 lore raw

PATCH 9/12 dt: socfpga: Import and enable Cyclone V DK DTS

Quoted 10 lines · Marek Vasut

Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#44 lore raw

PATCH 9/12 dt: socfpga: Import and enable Cyclone V DK DTS

In reply to Marek Vasut
Quoted 7 lines · Marek Vasut

Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#45 lore raw

PATCH 10/12 dt: socfpga: Import and enable Arria V DK DTS

In reply to Marek Vasut

Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/dts/Makefile                 |  1 +
 arch/arm/dts/socfpga_arria5.dtsi      | 34 ++++++++++++++++
 arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++++++++++++++++++++++++++++
 configs/socfpga_arria5_defconfig      |  2 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
arch/arm/dts/Makefile +1 -0
index c851d65..2a84323 100644
@@ -49,6 +49,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 dtb-$(CONFIG_SOCFPGA) +=				\
+	socfpga_arria5_socdk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_socrates.dtb
arch/arm/dts/socfpga_arria5.dtsi new file +34 -0
new file mode 100644
index 0000000..5175f03
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+	soc {
+		clkmgr at ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+			};
+		};
+
+		mmc0: dwmmc0 at ff704000 {
+			num-slots = <1>;
+			broken-cd;
+			bus-width = <4>;
+			cap-mmc-highspeed;
+			cap-sd-highspeed;
+		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd080c4>;
+		};
+	};
+};
arch/arm/dts/socfpga_arria5_socdk.dts new file +74 -0

74 lines not on this page · raw message

configs/socfpga_arria5_defconfig +2 -0
index f290042..f152e9d 100644
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
Signature · 1 line
2.1.3
#46 lore raw

PATCH 10/12 dt: socfpga: Import and enable Arria V DK DTS

Quoted 10 lines · Marek Vasut

Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#47 lore raw

PATCH 10/12 dt: socfpga: Import and enable Arria V DK DTS

In reply to Marek Vasut
Quoted 7 lines · Marek Vasut

Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#48 lore raw

PATCH 10/12 dt: socfpga: Import and enable Arria V DK DTS

In reply to Marek Vasut
Quoted 37 lines · Marek Vasut

Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 arch/arm/dts/Makefile                 |  1 +
 arch/arm/dts/socfpga_arria5.dtsi      | 34 ++++++++++++++++
 arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++++++++++++++++++++++++++++
 configs/socfpga_arria5_defconfig      |  2 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
arch/arm/dts/Makefile +1 -0
index c851d65..2a84323 100644
@@ -49,6 +49,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 dtb-$(CONFIG_SOCFPGA) +=				\
+	socfpga_arria5_socdk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_socrates.dtb
arch/arm/dts/socfpga_arria5.dtsi new file +0 -0
new file mode 100644
index 0000000..5175f03

arch/arm/dts/socfpga_arria5.dtsi line 2

Quoted 2 lines
arch/arm/dts/socfpga_arria5.dtsi new file +2 -0
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>

Nit: extra space before "Copyright".

Quoted 38 lines
arch/arm/dts/socfpga_arria5.dtsi new file +32 -0
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+	soc {
+		clkmgr at ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+			};
+		};
+
+		mmc0: dwmmc0 at ff704000 {
+			num-slots = <1>;
+			broken-cd;
+			bus-width = <4>;
+			cap-mmc-highspeed;
+			cap-sd-highspeed;
+		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd080c4>;
+		};
+	};
+};
arch/arm/dts/socfpga_arria5_socdk.dts new file +0 -0
new file mode 100644
index 0000000..4e529a1

arch/arm/dts/socfpga_arria5_socdk.dts line 2

Quoted 2 lines
arch/arm/dts/socfpga_arria5_socdk.dts new file +2 -0
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>

Same nit

Dinh

author
#49 lore raw

PATCH 10/12 dt: socfpga: Import and enable Arria V DK DTS

Quoted 1 line · Dinh Nguyen

On 12/31/14 1:14 PM, Marek Vasut wrote:

[...]

Quoted 10 lines

arch/arm/dts/socfpga_arria5.dtsi line 2

Quoted 8 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_arria5.dtsi new file mode 100644 index 0000000..5175f03

arch/arm/dts/socfpga_arria5.dtsi new file +2 -0
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>

Nit: extra space before "Copyright".

Hi!

Sorry for the late reply. This DTS comes from mainline Linux, so I wonder if it makes sense to diverge here, especially since this is just a comment. Diverging in the DTS files would make it more annoying in the long run, since checking the differences between Linux and U-Boot would spit this one false positive.

What do you think please ?

Best regards,
Marek Vasut

author
#50 lore raw

PATCH 11/12 arm: socfpga: Zap checkboard()

In reply to Marek Vasut

Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/socfpga.c   | 16 ----------------
 include/configs/socfpga_common.h |  2 +-
 2 files changed, 1 insertion(+), 17 deletions(-)
board/altera/socfpga/socfpga.c +0 -16
index a9c330d..2b2b63d 100644
@@ -19,22 +19,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * Print Board information
- */
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
-	puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
-#endif
-
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
-	puts("BOARD: Altera SoCFPGA Arria5 Board\n");
-#endif
-
-	return 0;
-}
-
-/*
  * Initialization function which happen at early stage of c code
  */
 int board_early_init_f(void)
include/configs/socfpga_common.h +1 -1
index 6b1f967..c2a4c72 100644
@@ -19,7 +19,7 @@
  * High level configuration
  */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
Signature · 1 line
2.1.3
#51 lore raw

PATCH 11/12 arm: socfpga: Zap checkboard()

Quoted 10 lines · Marek Vasut

Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#52 lore raw

PATCH 11/12 arm: socfpga: Zap checkboard()

In reply to Marek Vasut
Quoted 7 lines · Marek Vasut

Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#53 lore raw

PATCH 11/12 arm: socfpga: Zap checkboard()

In reply to Marek Vasut
Quoted 10 lines · Marek Vasut

Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 5 lines
---
 board/altera/socfpga/socfpga.c   | 16 ----------------
 include/configs/socfpga_common.h |  2 +-
 2 files changed, 1 insertion(+), 17 deletions(-)
Acked-by Dinh Nguyen <[email protected]>
author
#54 lore raw

PATCH 12/12 arm: socfpga: Zap board_early_init_f()

In reply to Marek Vasut

Zap this unused empty function, no point in having it.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
---
 board/altera/socfpga/socfpga.c   | 8 --------
 include/configs/socfpga_common.h | 1 -
 2 files changed, 9 deletions(-)
board/altera/socfpga/socfpga.c +0 -8
index 2b2b63d..20d2216 100644
@@ -19,14 +19,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * Initialization function which happen at early stage of c code
- */
-int board_early_init_f(void)
-{
-	return 0;
-}
-
-/*
  * Miscellaneous platform dependent initialisations
  */
 int board_init(void)
include/configs/socfpga_common.h +0 -1
index c2a4c72..5254e9b 100644
@@ -20,7 +20,6 @@
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
Signature · 1 line
2.1.3
#56 lore raw

PATCH 12/12 arm: socfpga: Zap board_early_init_f()

In reply to Marek Vasut
Quoted 5 lines · Marek Vasut

Zap this unused empty function, no point in having it.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#57 lore raw

PATCH 12/12 arm: socfpga: Zap board_early_init_f()

In reply to Marek Vasut
Quoted 8 lines · Marek Vasut

Zap this unused empty function, no point in having it.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Vince Bridgers <[email protected]>
Quoted 4 lines
---
 board/altera/socfpga/socfpga.c   | 8 --------
 include/configs/socfpga_common.h | 1 -
 2 files changed, 9 deletions(-)
Acked-by Dinh Nguyen <[email protected]>