ARM: atmel: at91sam9m10g45ek: enable SPL

Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system.

As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM.

Signed-off-by Bo Shen <[email protected]>

---

Changes in v2:
- This patch based on one patch from Simon Glass
- http://patchwork.ozlabs.org/patch/430240/
- remove the low level init code.
- correct the stack of corvus board.

  arch/arm/Kconfig                                |  1 +
  arch/arm/cpu/at91-common/spl_at91.c             |  6 +-
  arch/arm/cpu/at91-common/u-boot-spl-arm9.lds    | 48 +++++++++++++++
  board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
  configs/at91sam9m10g45ek_mmc_defconfig          |  5 +-
  configs/at91sam9m10g45ek_nandflash_defconfig    |  5 +-
  include/configs/at91sam9m10g45ek.h              | 58 ++++++++++++++++++
  7 files changed, 198 insertions(+), 5 deletions(-)

create mode 100644 arch/arm/cpu/at91-common/u-boot-spl-arm9.lds

arch/arm/Kconfig +1 -0

index 5eb1d03..f4788c6 100644
@@ -141,6 +141,7 @@ config TARGET_AT91SAM9263EK
  config TARGET_AT91SAM9M10G45EK
  	bool "Support at91sam9m10g45ek"
  	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
  config TARGET_AT91SAM9N12EK
  	bool "Support at91sam9n12ek"

arch/arm/cpu/at91-common/spl_at91.c +5 -1

index 89f588b..af6fc0d 100644
@@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
  {
  }
 
-void spl_board_init(void)
+void __weak spl_board_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
  {
  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 

arch/arm/cpu/at91-common/u-boot-spl-arm9.lds new file +48 -0

new file mode 100644
index 0000000..6f350a9
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		arch/arm/cpu/arm926ejs/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}

board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +80 -0

index b807ef9..4289179 100644
@@ -8,6 +8,7 @@
 
  #include <common.h>
  #include <asm/io.h>
+#include <asm/arch/clk.h>
  #include <asm/arch/at91sam9g45_matrix.h>
  #include <asm/arch/at91sam9_smc.h>
  #include <asm/arch/at91_common.h>

@@ -15,6 +16,7 @@
  #include <asm/arch/gpio.h>
  #include <asm/arch/clk.h>
  #include <lcd.h>
+#include <linux/mtd/nand.h>
  #include <atmel_lcdc.h>
  #include <atmel_mci.h>
  #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)

@@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
  }
  #endif
 
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+	 * test mode, so it needs do some action to exit test mode.
+	 */
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
  #ifdef CONFIG_CMD_USB
  static void at91sam9m10g45ek_usb_hw_init(void)
  {

configs/at91sam9m10g45ek_mmc_defconfig +3 -2

index 1681bc8..30d632d 100644
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
  CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_ARM=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y

configs/at91sam9m10g45ek_nandflash_defconfig +3 -2

index 61ae56e..b3de8a1 100644
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
  CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y

include/configs/at91sam9m10g45ek.h +58 -0

index db5d5ea..50778f9 100644
@@ -203,4 +203,62 @@
   */
  #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl-arm9.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC0
  #endif

Hello Bo,

Am 21.01.2015 10:45, schrieb Bo Shen:

Quoted 10 lines

Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system.

As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM.

Signed-off-by Bo Shen <[email protected]>

---

Quoted 5 lines

Changes in v2:
- This patch based on one patch from Simon Glass
- http://patchwork.ozlabs.org/patch/430240/
- remove the low level init code.
- correct the stack of corvus board.

You do not change, nor need to change now with the patch from Simon something for the corvus board!

Beside of that:

Acked-by Heiko Schocher <[email protected]>

bye,
Heiko