powerpc/t1024rdb: Add support for T1024RDB-PB

index 5a3100f..db50f81 100644
@@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_RESET	0xFF
 #define CPLD_LBMAP_SHIFT	0x03
 #define CPLD_BOOT_SEL	   0x80
+
+#define CPLD_PCIE_SGMII_MUX	0x80
+#define CPLD_OVERRIDE_BOOT_EN	0x01
+#define CPLD_OVERRIDE_MUX_EN	0x02 /* PCIE/2.5G-SGMII mux override enable */

index 2e400c4..f611ff0 100644
@@ -21,6 +21,7 @@
 #include <phy.h>
 #include <asm/fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
+#include "../common/fman.h"
 
 int board_eth_init(bd_t *bis)
 {

@@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+	/* Set the on-board RGMII PHY address */
 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
 	switch (srds_s1) {
 	case 0x95:
-		/* 10G XFI with Aquantia PHY */
+		/* set the on-board RGMII2  PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+		/* set 10G XFI with Aquantia AQR105 PHY */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		break;
+	case 0x77:
+	case 0x135:
+		/* set the on-board 2.5G SGMII AQR105 PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+		break;
 	default:
 		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
 		       srds_s1);

@@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
+		case PHY_INTERFACE_MODE_SGMII_2500:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
 		default:
 			break;
 		}

@@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
+	    (port == FM1_DTSEC3)) {
+		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+		fdt_setprop(fdt, offset, "phy-connection-type",
+			    "sgmii-2500", 10);
+		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+	}
+}
+
 void fdt_fixup_board_enet(void *fdt)
 {
 }

index f5c438d..9676577 100644
@@ -27,6 +27,11 @@ int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
 	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	printf("Board: %sRDB, ", cpu->name);
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",

@@ -50,11 +55,34 @@ int checkboard(void)
 #endif
 
 	puts("SERDES Reference Clocks:\n");
-	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	if (srds_s1 == 0x95)
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	else
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
 
 	return 0;
 }
 
+static void board_mux_lane(void)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+	u8 reg = CPLD_READ(misc_ctl_status);
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (srds_prtcl_s1 == 0x95) {
+		/* Route Lane B to PCIE */
+		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
+	} else {
+		/* Route Lane B to SGMII */
+		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
+	}
+	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE

@@ -86,6 +114,7 @@ int board_early_init_r(void)
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_portals();
 #endif
+	board_mux_lane();
 
 	return 0;
 }

index 6f1fcd6..9e71836 100644
@@ -743,8 +743,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
 #define RGMII_PHY1_ADDR		0x2
 #define RGMII_PHY2_ADDR		0x6
+#define SGMII_PHY1_ADDR		0x2
 #define FM1_10GEC1_PHY_ADDR	0x1
 #endif