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spl_mem_init.c : Added support for mDDR in SPL for i.MX28

PATCH New Marco Cavallini 3 participants 3 messages Feb 23, 2015 – Mar 3, 2015

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Arm (32-bit) Arm i.MX and Layerscape
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Marco Cavallini

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#0 lore raw

PATCH 1/1 spl_mem_init.c : Added support for mDDR in SPL for i.MX28

Signed-off-by Marco Cavallini <[email protected]>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +18 -0
index a744e5d..9e11288 100644
@@ -315,9 +315,27 @@ static void mx28_mem_init(void)
 
 	debug("SPL: Initialising mx28 SDRAM Controller\n");
 
+#ifndef CONFIG_SYS_MXS_mDDR
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+#else
+	/* Set mDDR mode */
+	writel(	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK,
+		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl);
+
+	/* Configure Pins 0-15 as EMI pins */
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel10);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel11);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel12);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel13);
+#endif
 
 	/*
 	 * Configure the DRAM registers
Signature · 1 line
1.7.9.5
reviewer
#1 lore raw

PATCH 1/1 spl_mem_init.c : Added support for mDDR in SPL for i.MX28

Hi Marco,

On Mon, Feb 23, 2015 at 11:34 AM, Marco Cavallini
<[email protected]> wrote:

Please provide a commit log.

Quoted 10 lines
Signed-off-by Marco Cavallini <[email protected]>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +0 -0
index a744e5d..9e11288 100644

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c static void mx28_mem_init(void) · line 318

Quoted 4 lines
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +1 -0
@@ -315,9 +315,27 @@ static void mx28_mem_init(void)
 
        debug("SPL: Initialising mx28 SDRAM Controller\n");
 
+#ifndef CONFIG_SYS_MXS_mDDR

Currently there is no user for this config option.

I suggest that you document it and add a board that makes use of it.

Regards,

Fabio Estevam

#2 lore raw

PATCH 1/1 spl_mem_init.c : Added support for mDDR in SPL for i.MX28

In reply to Marco Cavallini

Hi Marco,

Quoted 25 lines · Marco Cavallini
Signed-off-by Marco Cavallini <[email protected]>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +8 -0
index a744e5d..9e11288 100644
@@ -315,9 +315,27 @@ static void mx28_mem_init(void)
 
 	debug("SPL: Initialising mx28 SDRAM Controller\n");
 
+#ifndef CONFIG_SYS_MXS_mDDR
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+#else
+	/* Set mDDR mode */
+	writel(	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK |

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c static void mx28_mem_init(void) · line 338

Quoted 10 lines
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +10 -0
+		PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK,
+		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl);
+
+	/* Configure Pins 0-15 as EMI pins */
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel10);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel11);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel12);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel13);
+#endif

The thing is that there is no use case in mainline, because no board is using it. To avoid that the issue is completely hidden, I suggest to add at least documentation for CONFIG_SYS_MXS_mDDR in README. If someone else will use mDDR, it will be easy to find how.

Best regards,
Stefano Babic

Signature · 5 lines
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