ARM: mvebu: a385-db-ap: Enable the NAND
PATCH v5 1/1 ARM: mvebu: a385-db-ap: Enable the NAND
The Armada 385 Access Point Development Board has a 1GB NAND SLC chip from Micron as its main storage. Enable it.
Signed-off-by Maxime Ripard <[email protected]>
---
Changes from v4:
- Rebased on top of 4.0-rc1
arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/boot/dts/armada-385-db-ap.dts +13 -0
@@ -150,6 +150,19 @@ phy = <&phy0>; phy-mode = "rgmii-id"; }; + + nfc: flash at d0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; }; pcie-controller {
Signature · 1 line
2.3.0
PATCH v5 1/1 ARM: mvebu: a385-db-ap: Enable the NAND
Hi Maxime,
Quoted 2 lines · Maxime Ripard
The Armada 385 Access Point Development Board has a 1GB NAND SLC chip from Micron as its main storage. Enable it.
applied on mvebu/dt
Thanks,
Gregory
Quoted 34 lines
Signed-off-by Maxime Ripard <[email protected]>---
Changes from v4:
- Rebased on top of 4.0-rc1arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)arch/arm/boot/dts/armada-385-db-ap.dts +13
-0@@ -150,6 +150,19 @@ phy = <&phy0>; phy-mode = "rgmii-id"; }; + + nfc: flash at d0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; }; pcie-controller {
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com