powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
PATCH v2 1/1 powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHzTop level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous device's frequencies
(6) README added for the same
---
chnages in v2:
Incorporated review comments
All DSP aware code is enclosed with #ifdef
to not increase the uboot code size for other platforms Tested it on B4860QDS and on T4240QDS
arch/powerpc/cpu/mpc85xx/cpu.c | 28 ++++++ arch/powerpc/cpu/mpc85xx/speed.c | 140 +++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 91 ++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++- arch/powerpc/include/asm/processor.h | 5 + doc/README.Heterogeneous-SoCs | 105 +++++++++++++++++++++ include/common.h | 2 + include/e500.h | 11 +++ 8 files changed, 393 insertions(+), 3 deletions(-) create mode 100644 doc/README.Heterogeneous-SoCs
arch/powerpc/cpu/mpc85xx/cpu.c +28 -0
@@ -73,6 +73,11 @@ int checkcpu (void)unsigned int i, core, nr_cores =cpu_numcores ();u32 mask =cpu_mask (); +#ifdef CONFIG_HETROGENOUS_CLUSTERS +unsigned int j, dsp_core, dsp_numcores =cpu_num_dspcores (); +u32 dsp_mask =cpu_dsp_mask (); +#endif + svr =get_svr (); major =SVR_MAJ (svr); minor =SVR_MIN (svr);
@@ -166,6 +171,16 @@ int checkcpu (void)printf ("CPU%d:%-4s MHz, " , core,strmhz (buf1, sysinfo.freq_processor[core])); } + +#ifdef CONFIG_HETROGENOUS_CLUSTERS +for_each_cpu (j, dsp_core, dsp_numcores, dsp_mask) { +if (!(j &3 )) +printf ("\n " ); +printf ("DSP CPU%d:%-4s MHz, " , j, +strmhz (buf1, sysinfo.freq_processor_dsp[dsp_core])); + } +#endif +printf ("\n CCB:%-4s MHz," ,strmhz (buf1, sysinfo.freq_systembus));printf ("\n" );
@@ -224,6 +239,19 @@ int checkcpu (void)printf (" QE:%-4s MHz\n" ,strmhz (buf1, sysinfo.freq_qe));#endif +#if defined(CONFIG_SYS_CPRI ) +printf (" " ); +printf ("CPRI:%-4s MHz" ,strmhz (buf1, sysinfo.freq_cpri)); +#endif + +#if defined(CONFIG_SYS_MAPLE ) +printf ("\n " ); +printf ("MAPLE:%-4s MHz, " ,strmhz (buf1, sysinfo.freq_maple)); +printf ("MAPLE-ULB:%-4s MHz, " ,strmhz (buf1, sysinfo.freq_maple_ulb)); +printf ("MAPLE-eTVPE:%-4s MHz\n" , +strmhz (buf1, sysinfo.freq_maple_etvpe)); +#endif +#ifdef CONFIG_SYS_DPAA_FMAN for (i =0 ; i <CONFIG_SYS_NUM_FMAN ; i++) { printf(" FMAN%d: %s MHz\n", i + 1,
arch/powerpc/cpu/mpc85xx/speed.c +140 -0
164 lines not on this page · raw message
arch/powerpc/cpu/mpc8xxx/cpu.c +90 -1
116 lines not on this page · raw message
arch/powerpc/include/asm/config_mpc85xx.h +12 -2
@@ -689,13 +689,22 @@#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ +#define CONFIG_PPC_CLUSTER_START 0/*Start index of ppc clusters*/ +#define CONFIG_DSP_CLUSTER_START 1/*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_NUM_LAWS 32#define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_MAPLE +#define CONFIG_SYS_CPRI +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5#define CONFIG_SYS_FSL_SEC_COMPAT 4#define CONFIG_SYS_NUM_FMAN 1#define CONFIG_USB_MAX_CONTROLLER_COUNT 1#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_CPRI_CLK 3 +#define CONFIG_SYS_ULB_CLK 4 +#define CONFIG_SYS_ETVPE_CLK 1#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4#define CONFIG_SYS_FMAN_V3
@@ -718,8 +727,9 @@#ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4#define CONFIG_MAX_CPUS 4 +#define CONFIG_MAX_DSP_CPUS 12 +#define CONFIG_NUM_DSP_CPUS 6#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }#define CONFIG_SYS_NUM_FM1_DTSEC 6#define CONFIG_SYS_NUM_FM1_10GEC 2
@@ -731,9 +741,9 @@#define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_DSP_CPUS 2#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }#define CONFIG_SYS_NUM_FM1_DTSEC 4#define CONFIG_SYS_NUM_FM1_10GEC 0
arch/powerpc/include/asm/processor.h +5 -0
@@ -1202,12 +1202,17 @@ struct cpu_type {u32 soc_ver;u32 num_cores;u32 mask;/* which cpu(s) actually exist */ +#ifdef CONFIG_HETROGENOUS_CLUSTERS +u32 dsp_num_cores; +u32 dsp_mask;/* which DSP cpu(s) actually exist */ +#endif };struct cpu_type *identify_cpu (u32 ver);int fixup_cpu (void );int fsl_qoriq_core_to_cluster (unsigned int core); +int fsl_qoriq_dsp_core_to_cluster (unsigned int core);#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)#define CPU_TYPE_ENTRY (n, v, nc) \
doc/README.Heterogeneous-SoCs new file +105 -0
105 lines not on this page · raw message
include/common.h +2 -0
@@ -533,7 +533,9 @@ static inline int cpumask_next(int cpu, unsigned int mask) iter++, cpu = cpumask_next(cpu, mask)) \int cpu_numcores (void ); +int cpu_num_dspcores (void );u32 cpu_mask (void ); +u32 cpu_dsp_mask (void );int is_core_valid (unsigned int );int probecpu (void );int checkcpu (void );
include/e500.h +11 -0
@@ -11,6 +11,9 @@ typedef struct { unsigned long freq_processor[CONFIG_MAX_CPUS]; +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS]; +#endif unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus;
@@ -24,6 +27,14 @@ typedef struct#ifdef CONFIG_SYS_DPAA_PME unsigned long freq_pme;#endif +#ifdef CONFIG_SYS_CPRI +unsigned long freq_cpri; +#endif +#ifdef CONFIG_SYS_MAPLE +unsigned long freq_maple; +unsigned long freq_maple_ulb; +unsigned long freq_maple_etvpe; +#endif #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK unsigned char diff_sysclk;#endif
Signature · 1 line
1.7.6.GIT
PATCH v2 1/1 powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
Quoted 33 lines · Shaveta Leekha
The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHzTop level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask,cpu_num_dspcoresetc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous device's frequencies
(6) README added for the same
Quoted 8 lines
Signed-off-by Shaveta Leekha <[email protected]>---
chnages in v2:
Incorporated review comments
All DSP aware code is enclosed with #ifdef
to not increase the uboot code size for other platforms Tested it on B4860QDS and on T4240QDS
Applied to u-boot-mpc85xx master, awaiting for upstream.
York