Skip to contentSkip to conversation

mmc: fsl_esdhc: Add support for DDR mode

PATCH Superseded Volodymyr Riazantsev 4 participants 9 messages Jan 20, 2015 – Mar 12, 2015 MMC, SD and SDIO

lore
Share & tools
lore

Volodymyr Riazantsev

author
#0 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Change-Id Ie27a945c9fe79d044cc886e269b60747f1744116
Signed-off-by Volodymyr Riazantsev <[email protected]>
---
 drivers/mmc/fsl_esdhc.c      | 8 ++++++--
 include/configs/mx6_common.h | 2 ++
 include/fsl_esdhc.h          | 1 +
 3 files changed, 9 insertions(+), 2 deletions(-)
drivers/mmc/fsl_esdhc.c +6 -2
index c55eb28..f5d2ccb 100644
@@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 #if defined(CONFIG_FSL_USDHC)
 	esdhc_write32(&regs->mixctrl,
-	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 #else
 	esdhc_write32(&regs->xfertyp, xfertyp);

@@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 		if ((sdhc_clk / (div * pre_div)) <= clock)
 			break;
 
-	pre_div >>= 1;
+	pre_div >>= mmc->ddr_mode ? 2 : 1;
 	div -= 1;
 
 	clk = (pre_div << 8) | (div << 4);

@@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	}
 
 	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+	cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
 
 	if (cfg->max_bus_width > 0) {
 		if (cfg->max_bus_width < 8)
include/configs/mx6_common.h +2 -0
index e0528ce..29b72b2 100644
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
include/fsl_esdhc.h +1 -0
index c1b6648..313fa1e 100644
@@ -108,6 +108,7 @@
 #define XFERTYP_RSPTYP_48_BUSY	0x00030000
 #define XFERTYP_MSBSEL		0x00000020
 #define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_DDREN		0x00000008
 #define XFERTYP_AC12EN		0x00000004
 #define XFERTYP_BCEN		0x00000002
 #define XFERTYP_DMAEN		0x00000001
Signature · 1 line
2.2.0
#1 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Quoted 6 lines · Volodymyr Riazantsev

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Change-Id Ie27a945c9fe79d044cc886e269b60747f1744116
Signed-off-by Volodymyr Riazantsev <[email protected]>

---

Applied to u-boot-fsl-qoriq master branch, awaiting upstream.

York

#2 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Quoted 9 lines · York Sun
Quoted 6 lines · Volodymyr Riazantsev

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Change-Id Ie27a945c9fe79d044cc886e269b60747f1744116
Signed-off-by Volodymyr Riazantsev <[email protected]>

---

Applied to u-boot-fsl-qoriq master branch, awaiting upstream.

This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:

MMC write: dev # 0, block # 2, count 711 ... mmc write failed

With this patch reverted it looks just fine:

MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK

Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.

Thanks,
Stefan

#3 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Volodymyr,

Quoted 14 lines · Stefan Roese
Quoted 9 lines · York Sun
Quoted 6 lines · Volodymyr Riazantsev

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Change-Id Ie27a945c9fe79d044cc886e269b60747f1744116
Signed-off-by Volodymyr Riazantsev <[email protected]>

---

Applied to u-boot-fsl-qoriq master branch, awaiting upstream.

This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:

Quoted 8 lines

MMC write: dev # 0, block # 2, count 711 ... mmc write failed

With this patch reverted it looks just fine:

MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK

Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.

Please look into this issue and post a patch to fix if applicable. Thanks.

York

#4 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

In reply to Stefan Roese

Hi Stefan,

Quoted 11 lines · Stefan Roese

This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:

MMC write: dev # 0, block # 2, count 711 ... mmc write failed

With this patch reverted it looks just fine:

MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK

Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.

Does this fix from Peng help?
http://lists.denx.de/pipermail/u-boot/2015-March/207632.html

Regards,

Fabio Estevam

#5 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Hi Fabio,

Quoted 7 lines · Fabio Estevam
Quoted 7 lines

This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:

MMC write: dev # 0, block # 2, count 711 ... mmc write failed

With this patch reverted it looks just fine:

Quoted 7 lines
Quoted 4 lines

MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK

Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.

Does this fix from Peng help?
http://lists.denx.de/pipermail/u-boot/2015-March/207632.html

No, it does unfortunately not.

Thanks,
Stefan

#6 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

In reply to Volodymyr Riazantsev

Volodymyr,

include/configs/mx6_common.h line 31

Quoted 9 lines · Volodymyr Riazantsev
include/configs/mx6_common.h +1 -0
index e0528ce..29b72b2 100644
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_PL310_BASE  L2_PL310_BASE
 #endif
 
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE

Shouldn't this be defined per board config file instead?

Stefan,

Does your board work if CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE is removed from mx6_common.h?

Regards,

Fabio Estevam

author
#7 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Fabio,
Yes, it was too optimistic to enable it for all i.MX6 base devices,
I'll submit patch for disable it by default.
Vendors can enable it separately for custom boards.

Stefan,
Please let me know if you have any results with debug patches.

BR,
? Volodymyr.
<http://www.globallogic.com/email_disclaimer.txt>

Quoted 26 lines · Fabio Estevam

Volodymyr,

include/configs/mx6_common.h line 31

Quoted 9 lines · Volodymyr Riazantsev
include/configs/mx6_common.h +1 -0
index e0528ce..29b72b2 100644
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_PL310_BASE  L2_PL310_BASE
 #endif
 
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE

Shouldn't this be defined per board config file instead?

Stefan,

Does your board work if CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE is removed from mx6_common.h?

Regards,

Fabio Estevam

#8 lore raw

PATCH v2 1/1 mmc: fsl_esdhc: Add support for DDR mode

Hi Volodymyr,

Quoted 6 lines · Volodymyr Riazantsev

Yes, it was too optimistic to enable it for all i.MX6 base devices,
I'll submit patch for disable it by default.
Vendors can enable it separately for custom boards.

Stefan,
Please let me know if you have any results with debug patches.

I tought that I already send the debug output a few days ago. But here again.

Thanks,
Stefan

-------------- next part --------------
A non-text attachment was scrubbed...
Name: mmc-trace.log
Type: text/x-log
Size: 11348 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20150312/30d69485/attachment.bin>