Skip to contentSkip to conversation

ARM: atmel: boards: enable SPL support

PATCH Superseded Bo Shen 3 participants 10 messages Mar 13, 2015 – Mar 17, 2015

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/Microchip (AT91) SoC support

v1 of 2 Superseded Latest is v2 →

lore
Share & tools
lore

Bo Shen

author
#0 lore raw

cover ARM: atmel: boards: enable SPL support

This patch series enable SPL support for following boards:
- at91sam9m10g45ek
- NAND flash boot support
- SD card boot support
- at91sam9n12ek
- NAND flash boot support
- SPI flash boot support
- at91sam9x5ek
- NAND flash boot support
- SPI flash boot support

Bo Shen (4):
ARM: atmel: arm926ejs: fix clock configuration
ARM: atmel: at91sam9m10g45ek: enable spl support
ARM: atmel: at91sam9x5ek: enable spl support
ARM: atmel: at91sam9n12ek: enable spl support

 arch/arm/mach-at91/Kconfig                      |  3 +
 arch/arm/mach-at91/Makefile                     |  2 +
 arch/arm/mach-at91/arm926ejs/clock.c            | 54 +++++++++--------
 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds     | 48 +++++++++++++++
 arch/arm/mach-at91/include/mach/at91_pmc.h      |  6 +-
 arch/arm/mach-at91/include/mach/at91sam9x5.h    | 10 ++++
 arch/arm/mach-at91/mpddrc.c                     |  3 +-
 arch/arm/mach-at91/spl.c                        |  2 +-
 arch/arm/mach-at91/spl_at91.c                   | 11 +++-
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
 board/atmel/at91sam9n12ek/at91sam9n12ek.c       | 73 ++++++++++++++++++++++
 board/atmel/at91sam9x5ek/at91sam9x5ek.c         | 74 +++++++++++++++++++++++
 configs/at91sam9m10g45ek_mmc_defconfig          |  7 ++-
 configs/at91sam9m10g45ek_nandflash_defconfig    |  7 ++-
 configs/at91sam9n12ek_nandflash_defconfig       |  7 ++-
 configs/at91sam9n12ek_spiflash_defconfig        |  7 ++-
 configs/at91sam9x5ek_nandflash_defconfig        |  7 ++-
 configs/at91sam9x5ek_spiflash_defconfig         |  7 ++-
 include/configs/at91sam9m10g45ek.h              | 58 ++++++++++++++++++
 include/configs/at91sam9n12ek.h                 | 58 +++++++++++++++++-
 include/configs/at91sam9x5ek.h                  | 57 ++++++++++++++++++
 21 files changed, 531 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Signature · 1 line
2.3.0
author
#1 lore raw

PATCH 1/4 ARM: atmel: arm926ejs: fix clock configuration

Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed.

Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration.

Signed-off-by Bo Shen <[email protected]>

---

 arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 26 deletions(-)
arch/arm/mach-at91/arm926ejs/clock.c +28 -26
index f363982..8d6934e 100644
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
 void at91_plla_init(u32 pllar)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
 
 	writel(pllar, &pmc->pllar);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+		;
 }
 void at91_pllb_init(u32 pllbr)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
 
 	writel(pllbr, &pmc->pllbr);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
+		;
 }
 
 void at91_mck_init(u32 mckr)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
 	u32 tmp;
 
 	tmp = readl(&pmc->mckr);
-	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
-		 AT91_PMC_MCKR_MDIV_MASK |
-		 AT91_PMC_MCKR_PLLADIV_MASK |
-		 AT91_PMC_MCKR_CSS_MASK);
-	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
-		       AT91_PMC_MCKR_MDIV_MASK |
-		       AT91_PMC_MCKR_PLLADIV_MASK |
-		       AT91_PMC_MCKR_CSS_MASK);
+	tmp &= ~AT91_PMC_MCKR_PRES_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
 	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
 
-	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_CSS_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
 }
 
 void at91_periph_clk_enable(int id)
Signature · 1 line
2.3.0
#2 lore raw

PATCH 1/4 ARM: atmel: arm926ejs: fix clock configuration

Hello Bo,

Am 13.03.2015 10:19, schrieb Bo Shen:

Quoted 7 lines

Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed.

Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration.

Quoted 5 lines
Signed-off-by Bo Shen <[email protected]>

---

  arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
  1 file changed, 28 insertions(+), 26 deletions(-)

Tested on the corvus and taurus board.

Tested-by Heiko Schocher <[email protected]>
Quoted 8 lines
arch/arm/mach-at91/arm926ejs/clock.c +0 -0
index f363982..8d6934e 100644
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
  void at91_plla_init(u32 pllar)
  {
  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

arch/arm/mach-at91/arm926ejs/clock.c int at91_clock_init(unsigned long main_clock) · line 201

Quoted 10 lines
arch/arm/mach-at91/arm926ejs/clock.c +2 -6
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
 
  	writel(pllar, &pmc->pllar);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+		;

just hanging is maybe also bad ... could we hang with adding a

		if (timeout == 0) {
			debug("could not set PLL(A|B)\n");
			timeout = AT91_PLL_LOCK_TIMEOUT;
		}

Thinking about it ... have we setup here the debug uart already? If not, forget my comment

bye,
Heiko

Quoted 66 lines
arch/arm/mach-at91/arm926ejs/clock.c +26 -20
  }
  void at91_pllb_init(u32 pllbr)
  {
  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
 
  	writel(pllbr, &pmc->pllbr);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
+		;
  }
 
  void at91_mck_init(u32 mckr)
  {
  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	int timeout = AT91_PLL_LOCK_TIMEOUT;
  	u32 tmp;
 
  	tmp = readl(&pmc->mckr);
-	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
-		 AT91_PMC_MCKR_MDIV_MASK |
-		 AT91_PMC_MCKR_PLLADIV_MASK |
-		 AT91_PMC_MCKR_CSS_MASK);
-	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
-		       AT91_PMC_MCKR_MDIV_MASK |
-		       AT91_PMC_MCKR_PLLADIV_MASK |
-		       AT91_PMC_MCKR_CSS_MASK);
+	tmp &= ~AT91_PMC_MCKR_PRES_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
  	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
 
-	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
-		timeout--;
-		if (timeout == 0)
-			break;
-	}
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~AT91_PMC_MCKR_CSS_MASK;
+	tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
+	writel(tmp, &pmc->mckr);
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
  }
 
  void at91_periph_clk_enable(int id)
Signature · 2 lines
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
author
#3 lore raw

PATCH 1/4 ARM: atmel: arm926ejs: fix clock configuration

Hi Heiko,

Quoted 13 lines · Heiko Schocher

Hello Bo,

Am 13.03.2015 10:19, schrieb Bo Shen:

Quoted 10 lines

Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed.

Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration.

Signed-off-by Bo Shen <[email protected]>

---

Quoted 7 lines
Quoted 3 lines
  arch/arm/mach-at91/arm926ejs/clock.c | 54
+++++++++++++++++++-----------------
  1 file changed, 28 insertions(+), 26 deletions(-)

Tested on the corvus and taurus board.

Tested-by Heiko Schocher <[email protected]>

Thanks.

Quoted 22 lines
Quoted 9 lines
arch/arm/mach-at91/arm926ejs/clock.c +0 -0
index f363982..8d6934e 100644
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
  void at91_plla_init(u32 pllar)
  {
      struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

arch/arm/mach-at91/arm926ejs/clock.c int at91_clock_init(unsigned long main_clock) · line 201

Quoted 10 lines
arch/arm/mach-at91/arm926ejs/clock.c +2 -6
-    int timeout = AT91_PLL_LOCK_TIMEOUT;
 
      writel(pllar, &pmc->pllar);
-    while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
-        timeout--;
-        if (timeout == 0)
-            break;
-    }
+    while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+        ;

just hanging is maybe also bad ... could we hang with adding a

Quoted 7 lines
         if (timeout == 0) {
             debug("could not set PLL(A|B)\n");
             timeout = AT91_PLL_LOCK_TIMEOUT;
         }

Thinking about it ... have we setup here the debug uart already? If not, forget my comment

Yes the uart is not ready. And one more thing, if the clock is not setup correctly, then the system will run in abnormal status. So, I remove the timeout check here.

Best Regards,
Bo Shen

Quoted 69 lines

bye,
Heiko

Quoted 66 lines
arch/arm/mach-at91/arm926ejs/clock.c +26 -20
  }
  void at91_pllb_init(u32 pllbr)
  {
      struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-    int timeout = AT91_PLL_LOCK_TIMEOUT;
 
      writel(pllbr, &pmc->pllbr);
-    while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
-        timeout--;
-        if (timeout == 0)
-            break;
-    }
+    while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
+        ;
  }
 
  void at91_mck_init(u32 mckr)
  {
      struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-    int timeout = AT91_PLL_LOCK_TIMEOUT;
      u32 tmp;
 
      tmp = readl(&pmc->mckr);
-    tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
-         AT91_PMC_MCKR_MDIV_MASK |
-         AT91_PMC_MCKR_PLLADIV_MASK |
-         AT91_PMC_MCKR_CSS_MASK);
-    tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
-               AT91_PMC_MCKR_MDIV_MASK |
-               AT91_PMC_MCKR_PLLADIV_MASK |
-               AT91_PMC_MCKR_CSS_MASK);
+    tmp &= ~AT91_PMC_MCKR_PRES_MASK;
+    tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
      writel(tmp, &pmc->mckr);
+    while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+        ;
 
-    while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
-        timeout--;
-        if (timeout == 0)
-            break;
-    }
+    tmp = readl(&pmc->mckr);
+    tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
+    tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
+    writel(tmp, &pmc->mckr);
+    while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+        ;
+
+    tmp = readl(&pmc->mckr);
+    tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
+    tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
+    writel(tmp, &pmc->mckr);
+    while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+        ;
+
+    tmp = readl(&pmc->mckr);
+    tmp &= ~AT91_PMC_MCKR_CSS_MASK;
+    tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
+    writel(tmp, &pmc->mckr);
+    while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+        ;
  }
 
  void at91_periph_clk_enable(int id)
#4 lore raw

PATCH 1/4 ARM: atmel: arm926ejs: fix clock configuration

Hello Bo,

Am 17.03.2015 08:58, schrieb Bo Shen:

Quoted 53 lines

Hi Heiko,

Quoted 13 lines · Heiko Schocher

Hello Bo,

Am 13.03.2015 10:19, schrieb Bo Shen:

Quoted 10 lines

Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed.

Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration.

Signed-off-by Bo Shen <[email protected]>

---

Quoted 7 lines
Quoted 3 lines
  arch/arm/mach-at91/arm926ejs/clock.c | 54
+++++++++++++++++++-----------------
  1 file changed, 28 insertions(+), 26 deletions(-)

Tested on the corvus and taurus board.

Tested-by Heiko Schocher <[email protected]>

Thanks.

Quoted 27 lines
Quoted 9 lines
arch/arm/mach-at91/arm926ejs/clock.c +0 -0
index f363982..8d6934e 100644
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
  void at91_plla_init(u32 pllar)
  {
      struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

arch/arm/mach-at91/arm926ejs/clock.c int at91_clock_init(unsigned long main_clock) · line 201

Quoted 10 lines
arch/arm/mach-at91/arm926ejs/clock.c +2 -6
-    int timeout = AT91_PLL_LOCK_TIMEOUT;
 
      writel(pllar, &pmc->pllar);
-    while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
-        timeout--;
-        if (timeout == 0)
-            break;
-    }
+    while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+        ;

just hanging is maybe also bad ... could we hang with adding a

         if (timeout == 0) {
             debug("could not set PLL(A|B)\n");
             timeout = AT91_PLL_LOCK_TIMEOUT;
         }
Quoted 4 lines
Quoted 2 lines

Thinking about it ... have we setup here the debug uart already? If not, forget my comment

Yes the uart is not ready. And one more thing, if the clock is not setup correctly, then the system will run in abnormal status. So, I remove the timeout check here.

Ok, thanks!

bye,
Heiko

Signature · 2 lines
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
author
#5 lore raw

PATCH 2/4 ARM: atmel: at91sam9m10g45ek: enable spl support

In reply to Bo Shen

Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system.

As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM.

Signed-off-by Bo Shen <[email protected]>

---

 arch/arm/mach-at91/Kconfig                      |  1 +
 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds     | 48 +++++++++++++++
 arch/arm/mach-at91/spl_at91.c                   |  6 +-
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
 configs/at91sam9m10g45ek_mmc_defconfig          |  7 ++-
 configs/at91sam9m10g45ek_nandflash_defconfig    |  7 ++-
 include/configs/at91sam9m10g45ek.h              | 58 ++++++++++++++++++
 7 files changed, 200 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
arch/arm/mach-at91/Kconfig +1 -0
index 30945c1..25da926 100644
@@ -66,6 +66,7 @@ config TARGET_STAMP9G20
 config TARGET_AT91SAM9M10G45EK
 	bool "Atmel AT91SAM9M10G45-EK board"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_PM9G45
 	bool "Ronetix pm9g45 board"
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds new file +48 -0

48 lines not on this page · raw message

arch/arm/mach-at91/spl_at91.c +5 -1
index 89f588b..af6fc0d 100644
@@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
 {
 }
 
-void spl_board_init(void)
+void __weak spl_board_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +80 -0

98 lines not on this page · raw message

configs/at91sam9m10g45ek_mmc_defconfig +4 -3
index 6949d3a..84d3133 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
configs/at91sam9m10g45ek_nandflash_defconfig +4 -3
index 30967e3..5bcb0f7 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
include/configs/at91sam9m10g45ek.h +58 -0

62 lines not on this page · raw message

Signature · 1 line
2.3.0
#6 lore raw

PATCH 2/4 ARM: atmel: at91sam9m10g45ek: enable spl support

Hi Bo,

2015-03-13 18:19 GMT+09:00 Bo Shen <[email protected]>:

configs/at91sam9m10g45ek_mmc_defconfig line 5

Quoted 13 lines
configs/at91sam9m10g45ek_mmc_defconfig +4 -3
index 6949d3a..84d3133 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y

I abolished the prefixes such "+S".
Now they are harmless, but meaningless.

I am ripping off all of them:
http://patchwork.ozlabs.org/patch/449347/

Could you please not change those three lines?

Signature · 2 lines
Best Regards
Masahiro Yamada
author
#7 lore raw

PATCH 2/4 ARM: atmel: at91sam9m10g45ek: enable spl support

Hi Masahiro,

Quoted 22 lines · Masahiro Yamada

Hi Bo,

2015-03-13 18:19 GMT+09:00 Bo Shen <[email protected]>:

configs/at91sam9m10g45ek_mmc_defconfig line 5

Quoted 13 lines
configs/at91sam9m10g45ek_mmc_defconfig +4 -3
index 6949d3a..84d3133 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
  CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y

I abolished the prefixes such "+S".
Now they are harmless, but meaningless.

Quoted 4 lines

I am ripping off all of them:
http://patchwork.ozlabs.org/patch/449347/

Could you please not change those three lines?

Thanks.

I will remove this change in next version.
Thanks again.

Best Regards,
Bo Shen

author
#8 lore raw

PATCH 3/4 ARM: atmel: at91sam9x5ek: enable spl support

In reply to Bo Shen

Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash.

Signed-off-by Bo Shen <[email protected]>

---

 arch/arm/mach-at91/Kconfig                   |  1 +
 arch/arm/mach-at91/Makefile                  |  1 +
 arch/arm/mach-at91/include/mach/at91_pmc.h   |  6 ++-
 arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++
 arch/arm/mach-at91/mpddrc.c                  |  3 +-
 arch/arm/mach-at91/spl.c                     |  2 +-
 arch/arm/mach-at91/spl_at91.c                |  5 ++
 board/atmel/at91sam9x5ek/at91sam9x5ek.c      | 74 ++++++++++++++++++++++++++++
 configs/at91sam9x5ek_nandflash_defconfig     |  7 +--
 configs/at91sam9x5ek_spiflash_defconfig      |  7 +--
 include/configs/at91sam9x5ek.h               | 57 +++++++++++++++++++++
 11 files changed, 163 insertions(+), 10 deletions(-)
arch/arm/mach-at91/Kconfig +1 -0
index 25da926..bdf87f9 100644
@@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK
 config TARGET_AT91SAM9X5EK
 	bool "Atmel AT91SAM9X5-EK board"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_SAMA5D3_XPLAINED
 	bool "SAMA5D3 Xplained board"
arch/arm/mach-at91/Makefile +1 -0
index e596ba6..ba83616 100644
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 ifneq ($(CONFIG_SPL_BUILD),)
 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
 obj-y += spl.o
arch/arm/mach-at91/include/mach/at91_pmc.h +4 -2
index 65691ab..c903260 100644
@@ -97,7 +97,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
 
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+	defined(CONFIG_AT91SAM9X5)
 #define AT91_PMC_MCKR_PRES_1		0x00000000
 #define AT91_PMC_MCKR_PRES_2		0x00000010
 #define AT91_PMC_MCKR_PRES_4		0x00000020

@@ -126,7 +127,8 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
 #define AT91_PMC_MCKR_MDIV_2		0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+	defined(CONFIG_AT91SAM9X5)
 #define AT91_PMC_MCKR_MDIV_3		0x00000300
 #endif
 #define AT91_PMC_MCKR_MDIV_4		0x00000200
arch/arm/mach-at91/include/mach/at91sam9x5.h +10 -0
index 36a5cdf..d18c936 100644
@@ -124,6 +124,16 @@
 #define ATMEL_BASE_EHCI		0x00700000 /* USB Host controller (EHCI) */
 #endif
 
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_CS1		0x20000000
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+
 /* 9x5 series chip id definitions */
 #define ARCH_ID_AT91SAM9X5	0x819a05a0
 #define ARCH_ID_VERSION_MASK	0x1f
arch/arm/mach-at91/mpddrc.c +2 -1
index beec13d..24d5fcd 100644
@@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+	defined(CONFIG_AT91SAM9X5)
 	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
 		return 0;
 #endif
arch/arm/mach-at91/spl.c +1 -1
index aaa5eec..27a405a 100644
@@ -29,7 +29,7 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_MMC1;
 #elif CONFIG_SYS_USE_NANDFLASH
 	return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH
+#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
 	return BOOT_DEVICE_SPI;
 #endif
 	return BOOT_DEVICE_NONE;
arch/arm/mach-at91/spl_at91.c +5 -0
index af6fc0d..e28e568 100644
@@ -115,9 +115,14 @@ void board_init_f(ulong dummy)
 	timer_init();
 
 	/* enable clocks for all PIOs */
+#ifdef CONFIG_AT91SAM9X5
+	at91_periph_clk_enable(ATMEL_ID_PIOAB);
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
+#else
 	at91_periph_clk_enable(ATMEL_ID_PIOA);
 	at91_periph_clk_enable(ATMEL_ID_PIOB);
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
+#endif
 	/* init console */
 	at91_seriald_hw_init();
 	preloader_console_init();
board/atmel/at91sam9x5ek/at91sam9x5ek.c +74 -0

77 lines not on this page · raw message

configs/at91sam9x5ek_nandflash_defconfig +4 -3
index c2ebb00..2303cb4 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9X5EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9X5EK=y
configs/at91sam9x5ek_spiflash_defconfig +4 -3
index 76f68a6..538f0c1 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9X5EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9X5EK=y
include/configs/at91sam9x5ek.h +57 -0

61 lines not on this page · raw message

Signature · 1 line
2.3.0
author
#9 lore raw

PATCH 4/4 ARM: atmel: at91sam9n12ek: enable spl support

In reply to Bo Shen

Enable SPL support for at91sam9n12ek boards, now it supports boot up from NAND flash, serial flash.

Signed-off-by Bo Shen <[email protected]>

---

 arch/arm/mach-at91/Kconfig                 |  1 +
 arch/arm/mach-at91/Makefile                |  1 +
 arch/arm/mach-at91/include/mach/at91_pmc.h |  4 +-
 arch/arm/mach-at91/mpddrc.c                |  2 +-
 arch/arm/mach-at91/spl_at91.c              |  2 +-
 board/atmel/at91sam9n12ek/at91sam9n12ek.c  | 73 ++++++++++++++++++++++++++++++
 configs/at91sam9n12ek_nandflash_defconfig  |  7 +--
 configs/at91sam9n12ek_spiflash_defconfig   |  7 +--
 include/configs/at91sam9n12ek.h            | 58 +++++++++++++++++++++++-
 9 files changed, 144 insertions(+), 11 deletions(-)
arch/arm/mach-at91/Kconfig +1 -0
index bdf87f9..30c4e17 100644
@@ -75,6 +75,7 @@ config TARGET_PM9G45
 config TARGET_AT91SAM9N12EK
 	bool "Atmel AT91SAM9N12-EK board"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_AT91SAM9RLEK
 	bool "Atmel at91sam9rl reference board"
arch/arm/mach-at91/Makefile +1 -0
index ba83616..0d3ee48 100644
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 ifneq ($(CONFIG_SPL_BUILD),)
 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
arch/arm/mach-at91/include/mach/at91_pmc.h +2 -2
index c903260..ebb7dec 100644
@@ -98,7 +98,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
 
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-	defined(CONFIG_AT91SAM9X5)
+	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_PRES_1		0x00000000
 #define AT91_PMC_MCKR_PRES_2		0x00000010
 #define AT91_PMC_MCKR_PRES_4		0x00000020

@@ -128,7 +128,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
 #define AT91_PMC_MCKR_MDIV_2		0x00000100
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-	defined(CONFIG_AT91SAM9X5)
+	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_MDIV_3		0x00000300
 #endif
 #define AT91_PMC_MCKR_MDIV_4		0x00000200
arch/arm/mach-at91/mpddrc.c +1 -1
index 24d5fcd..e2b6a49 100644
@@ -20,7 +20,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 static int ddr2_decodtype_is_seq(u32 cr)
 {
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-	defined(CONFIG_AT91SAM9X5)
+	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
 		return 0;
 #endif
arch/arm/mach-at91/spl_at91.c +1 -1
index e28e568..a79a9dc 100644
@@ -115,7 +115,7 @@ void board_init_f(ulong dummy)
 	timer_init();
 
 	/* enable clocks for all PIOs */
-#ifdef CONFIG_AT91SAM9X5
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 	at91_periph_clk_enable(ATMEL_ID_PIOAB);
 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 #else
board/atmel/at91sam9n12ek/at91sam9n12ek.c +73 -0

76 lines not on this page · raw message

configs/at91sam9n12ek_nandflash_defconfig +4 -3
index f908246..8d003ef 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9N12EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9N12EK=y
configs/at91sam9n12ek_spiflash_defconfig +4 -3
index d106b5a..cddebe7 100644
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9N12EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9N12EK=y
include/configs/at91sam9n12ek.h +57 -1

63 lines not on this page · raw message

Signature · 1 line
2.3.0