irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
Subsystems (7)
v6 cover irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
This series is extracted from [4], which is trying to remove all traces of gic_arch_extn from the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.
This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
It is worth realizing that:
- I haven't been able to test this as much as I would have wanted to (it's only been tested on omap4 and omap5).
- This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees...
Based on 4.0-rc1.
* From v5: [5]
- Allow interrupt affinity to be changed
* From v4: [4]
- Extracted from the full series
- Rebased on 4.0-rc1
* From v3 [3]:
- Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
- Fixed more iMX6 DTs (Stephan)
- Fixed Exynos4/5 DTs
* From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan
* From v1 [1]:
- Rebased on 3.19-rc3
- Fixed a number of additional platforms
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth
[5]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325178.html
[4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html
[3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
[2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
[1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html
Marc Zyngier (7):
genirq: Add irqchip_set_wake_parent
irqchip: crossbar: convert dra7 crossbar to stacked domains
DT: update ti,irq-crossbar binding
irqchip: GIC: get rid of routable domain
DT: arm,gic: kill arm,routable-irqs
DT: omap4/5: add binding for the wake-up generator
ARM: omap: convert wakeupgen to stacked domains
Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++--------- drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.h
Signature · 1 line
2.1.4
PATCH v6 1/7 genirq: Add irqchip_set_wake_parent
This proves to be useful with stacked domains, when the current domain doesn't implement wake-up, but expect the parent to do so.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- include/linux/irq.h | 1 + kernel/irq/chip.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+)
include/linux/irq.h +1 -0
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);extern int irq_chip_set_affinity_parent (struct irq_data *data,const struct cpumask *dest,bool force); +extern int irq_chip_set_wake_parent (struct irq_data *data,unsigned int on);#endif /* Handling of unhandled and spurious interrupts: */
kernel/irq/chip.c +16 -0
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data) return -ENOSYS; } + +/** +* irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt +* @data: Pointer to interrupt specific data +* @on: Whether to set or reset the wake-up capability of this irq +* +* Conditional, as the underlying parent chip might not implement it. +*/ +int irq_chip_set_wake_parent (struct irq_data *data,unsigned int on) +{ + data = data->parent_data; +if (data->chip->irq_set_wake) +return data->chip->irq_set_wake (data, on); + +return -ENOSYS ; +}#endif /**
Signature · 1 line
2.1.4
PATCH v6 2/7 irqchip: crossbar: convert dra7 crossbar to stacked domains
In reply to Marc ZyngierSupport for the TI crossbar used on the DRA7 family of chips is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the fact that this is actually yet another interrupt controller (the third, actually), we have yet another breakage. Oh well.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 35 +++--- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/mach-omap2/omap4-common.c | 4 - drivers/irqchip/irq-crossbar.c | 210 +++++++++++++++++++------------- include/linux/irqchip/irq-crossbar.h | 11 -- 9 files changed, 149 insertions(+), 125 deletions(-) delete mode 100644 include/linux/irqchip/irq-crossbar.h
arch/arm/boot/dts/am57xx-beagle-x15.dts +1 -2
@@ -454,7 +454,6 @@ mcp_rtc: rtc at 6f { compatible = "microchip,mcp7941x"; reg = <0x6f>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ pinctrl-names = "default";
@@ -477,7 +476,7 @@ &uart3 { status = "okay"; - interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x248>; pinctrl-names = "default";
arch/arm/boot/dts/dra7-evm.dts +1 -1
@@ -446,7 +446,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; - interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; };
arch/arm/boot/dts/dra7.dtsi +19 -16
@@ -13,14 +13,13 @@ #include "skeleton.dtsi" #define MAX_SOURCES 400 -#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) / { #address-cells = <1>; #size-cells = <1>; compatible = "ti,dra7xx"; - interrupt-parent = <&gic>; + interrupt-parent = <&crossbar_mpu>; aliases { i2c0 = &i2c1;
@@ -50,18 +49,19 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; }; gic: interrupt-controller at 48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; - arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, <0x48216000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; }; /*
@@ -91,8 +91,8 @@ ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x44000000 0x1000000>, <0x45000000 0x1000>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; prm: prm at 4ae06000 { compatible = "ti,dra7-prm";
@@ -344,7 +344,7 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled";
@@ -355,7 +355,7 @@ uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled";
@@ -366,7 +366,7 @@ uart3: serial at 48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled";
@@ -377,7 +377,7 @@ uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled";
@@ -388,7 +388,7 @@ uart5: serial at 48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled";
@@ -399,7 +399,7 @@ uart6: serial at 48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled";
@@ -410,7 +410,7 @@ uart7: serial at 48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; - interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled";
@@ -419,7 +419,7 @@ uart8: serial at 48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; - interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled";
@@ -428,7 +428,7 @@ uart9: serial at 48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; - interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled";
@@ -437,7 +437,7 @@ uart10: serial at 4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; - interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled";
@@ -1337,9 +1337,12 @@ status = "disabled"; }; - crossbar_mpu: crossbar at 4a020000 { + crossbar_mpu: crossbar at 4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; ti,max-irqs = <160>; ti,max-crossbar-sources = <MAX_SOURCES>; ti,reg-size = <2>;
arch/arm/boot/dts/dra72-evm.dts +0 -1
@@ -160,7 +160,6 @@ pinctrl-0 = <&tps65917_pins_default>; interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <2>;
arch/arm/boot/dts/dra72x.dtsi +2 -1
@@ -25,6 +25,7 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; }; };
arch/arm/boot/dts/dra74x.dtsi +3 -2
@@ -41,8 +41,9 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; }; ocp {
arch/arm/mach-omap2/omap4-common.c +0 -4
@@ -22,7 +22,6 @@#include <linux/of_platform.h> #include <linux/export.h> #include <linux/irqchip/arm-gic.h> -#include <linux/irqchip/irq-crossbar.h> #include <linux/of_address.h> #include <linux/reboot.h> #include <linux/genalloc.h>
@@ -292,8 +291,5 @@ void __init omap_gic_of_init(void) skip_errata_init:omap_wakeupgen_init (); -#ifdef CONFIG_IRQ_CROSSBAR -irqcrossbar_init (); -#endif irqchip_init (); }
drivers/irqchip/irq-crossbar.c +123 -87
301 lines not on this page · raw message
include/linux/irqchip/irq-crossbar.h deleted +0 -11
@@ -1,11 +0,0 @@ -/* -* drivers/irqchip/irq-crossbar.h -* -* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -*/ -int irqcrossbar_init (void );
Signature · 1 line
2.1.4
PATCH v6 3/7 DT: update ti,irq-crossbar binding
In reply to Marc ZyngierMake it look like a real interrupt controller.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- .../devicetree/bindings/arm/omap/crossbar.txt | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-)
Documentation/devicetree/bindings/arm/omap/crossbar.txt +5 -13
@@ -9,7 +9,9 @@ inputs. Required properties: - compatible : Should be "ti,irq-crossbar" - reg: Base address and the size of the crossbar registers. -- ti,max-irqs: Total number of irqs available at the interrupt controller. +- interrupt-controller: indicates that this block is an interrupt controller. +- interrupt-parent: the interrupt controller this block is connected to. +- ti,max-irqs: Total number of irqs available at the parent interrupt controller. - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. - ti,reg-size: Size of a individual register in bytes. Every individual register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties: when the interrupt controller irq is unused (when not provided, default is 0) Examples: - crossbar_mpu: @4a020000 { + crossbar_mpu: crossbar at 4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; ti,max-irqs = <160>; ti,max-crossbar-sources = <400>; ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; ti,irqs-skip = <10 133 139 140>; };
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details. An interrupt consumer on an SoC using crossbar will use: interrupts = <GIC_SPI request_number interrupt_level> -When the request number is between 0 to that described by -"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the -request_number is greater than "ti,max-crossbar-sources", then it is mapped as a -quirky hardware mapping direct to GIC. Example: device_x at 0x4a023000 {
@@ -55,9 +53,3 @@ Example: interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; ... }; - - device_y at 0x4a033000 { - /* Direct mapped GIC SPI 1 used */ - interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>; - ... - };
Signature · 1 line
2.1.4
PATCH v6 4/7 irqchip: GIC: get rid of routable domain
In reply to Marc ZyngierThe only user of the so called "routable domain" functionality now being fixed, let's clean up the GIC.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- drivers/irqchip/irq-gic.c | 59 ++++------------------------------------- include/linux/irqchip/arm-gic.h | 6 ----- 2 files changed, 5 insertions(+), 60 deletions(-)
drivers/irqchip/irq-gic.c +5 -54
@@ -798,15 +798,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,irq_domain_set_info (d, irq, hw, &gic_chip, d->host_data, handle_fasteoi_irq,NULL ,NULL );set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); - - gic_routable_irq_domain_ops->map (d, irq, hw); }return 0 ; }static void gic_irq_domain_unmap (struct irq_domain *d,unsigned int irq) { - gic_routable_irq_domain_ops->unmap (d, irq); } static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -825,16 +822,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d, *out_hwirq = intspec[1 ] +16 ;/* For SPIs, we need to add 16 more to get the GIC irq ID number */ -if (!intspec[0 ]) { - ret = gic_routable_irq_domain_ops->xlate (d, controller, - intspec, - intsize, - out_hwirq, - out_type); - -if (IS_ERR_VALUE (ret)) -return ret; - } +if (!intspec[0 ]) + *out_hwirq +=16 ; *out_type = intspec[2 ] &IRQ_TYPE_SENSE_MASK ;
@@ -891,37 +880,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .xlate = gic_irq_domain_xlate, }; -/* Default functions for routable irq domain */ -static int gic_routable_irq_domain_map (struct irq_domain *d,unsigned int irq, -irq_hw_number_t hw) -{ -return 0 ; -} - -static void gic_routable_irq_domain_unmap (struct irq_domain *d, -unsigned int irq) -{ -} - -static int gic_routable_irq_domain_xlate (struct irq_domain *d, -struct device_node *controller, -const u32 *intspec,unsigned int intsize, -unsigned long *out_hwirq, -unsigned int *out_type) -{ - *out_hwirq +=16 ; -return 0 ; -} - -static const struct irq_domain_ops gic_default_routable_irq_domain_ops = { - .map = gic_routable_irq_domain_map, - .unmap = gic_routable_irq_domain_unmap, - .xlate = gic_routable_irq_domain_xlate, -}; - -const struct irq_domain_ops *gic_routable_irq_domain_ops = - &gic_default_routable_irq_domain_ops; -void __init gic_init_bases (unsigned int gic_nr,int irq_start,void __iomem *dist_base,void __iomem *cpu_base,u32 percpu_offset,struct device_node *node)
@@ -929,7 +887,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,irq_hw_number_t hwirq_base;struct gic_chip_data *gic;int gic_irqs, irq_base, i; -int nr_routable_irqs;BUG_ON (gic_nr >=MAX_GIC_NR );
@@ -985,15 +942,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic->gic_irqs = gic_irqs;if (node) {/* DT case */ -const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops; - -if (!of_property_read_u32 (node,"arm,routable-irqs" , - &nr_routable_irqs)) { - ops = &gic_irq_domain_ops; - gic_irqs = nr_routable_irqs; - } - - gic->domain =irq_domain_add_linear (node, gic_irqs, ops, gic); + gic->domain =irq_domain_add_linear (node, gic_irqs, + &gic_irq_domain_hierarchy_ops, + gic); }else {/* Non-DT case */ /* * For primary GICs, skip over SGIs.
include/linux/irqchip/arm-gic.h +0 -6
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);void gic_migrate_target (unsigned int new_cpu_id);unsigned long gic_get_sgir_physaddr (void ); -extern const struct irq_domain_ops *gic_routable_irq_domain_ops; -static inline void __init register_routable_domain_ops - (const struct irq_domain_ops *ops) -{ - gic_routable_irq_domain_ops = ops; -}#endif /* __ASSEMBLY */ #endif
Signature · 1 line
2.1.4
PATCH v6 5/7 DT: arm,gic: kill arm,routable-irqs
In reply to Marc ZyngierNobody will regret it.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- Documentation/devicetree/bindings/arm/gic.txt | 6 ------ 1 file changed, 6 deletions(-)
Documentation/devicetree/bindings/arm/gic.txt +0 -6
@@ -56,11 +56,6 @@ Optional regions, used when the GIC doesn't have banked registers. The offset is cpu-offset * cpu-nr. -- arm,routable-irqs : Total number of gic irq inputs which are not directly - connected from the peripherals, but are routed dynamically - by a crossbar/multiplexer preceding the GIC. The GIC irq - input line is assigned dynamically when the corresponding - peripheral's crossbar line is mapped. Example: intc: interrupt-controller at fff11000 {
@@ -68,7 +63,6 @@ Example: #interrupt-cells = <3>; #address-cells = <1>; interrupt-controller; - arm,routable-irqs = <160>; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; };
Signature · 1 line
2.1.4
PATCH v6 6/7 DT: omap4/5: add binding for the wake-up generator
In reply to Marc ZyngierAdd a binding for the OMAP4/5 wake-up generator, which acts as an interrupt controller feeding into the GIC.
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu new file +33 -0
@@ -0,0 +1,33 @@ +TI OMAP4 Wake-up Generator + +All TI OMAP4/5 (and their derivatives) an interrupt controller that +routes interrupts to the GIC, and also serves as a wakeup source. It +is also referred to as "WUGEN-MPU", hence the name of the binding. + +Reguired properties: + +- compatible : should contain at least "ti,omap4-wugen-mpu" or + "ti,omap5-wugen-mpu" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : a phandle to the GIC these interrupts are routed + to. + +Notes: + +- Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. +- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs + are explicitly forbiden. + +Example: + + wakeupgen: interrupt-controller at 48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; + };
Signature · 1 line
2.1.4
PATCH v6 7/7 ARM: omap: convert wakeupgen to stacked domains
In reply to Marc ZyngierOMAP4/5 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead.
This patch does just this, updating the DT files to actually reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not exposing the WUGEN HW block, kernels with this patch applied won't have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like this:
root at bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer 19: 233799 155916 GIC 27 arch_timer 23: 0 0 WUGEN 9 l3-dbg-irq 24: 1 0 WUGEN 10 l3-app-irq 27: 282 0 WUGEN 13 omap-dma-engine 44: 0 0 4ae10000.gpio 13 DMA 294: 0 0 WUGEN 20 gpmc 297: 506 0 WUGEN 56 48070000.i2c 298: 0 0 WUGEN 57 48072000.i2c 299: 0 0 WUGEN 61 48060000.i2c 300: 0 0 WUGEN 62 4807a000.i2c 301: 8 0 WUGEN 60 4807c000.i2c 308: 2439 0 WUGEN 74 OMAP UART2 312: 362 0 WUGEN 83 mmc2 313: 502 0 WUGEN 86 mmc0 314: 13 0 WUGEN 94 mmc1 350: 0 0 PRCM pinctrl, pinctrl 406: 35155709 0 GIC 109 ehci_hcd:usb1 407: 0 0 WUGEN 7 palmas 409: 0 0 WUGEN 119 twl6040 410: 0 0 twl6040 5 twl6040_irq_ready 411: 0 0 twl6040 0 twl6040_irq_th IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 95334 902334 Rescheduling interrupts IPI3: 0 0 Function call interrupts IPI4: 479 648 Single function call interrupts IPI5: 0 0 CPU stop interrupts IPI6: 0 0 IRQ work interrupts IPI7: 0 0 completion interrupts Err: 0
Acked-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
--- arch/arm/boot/dts/am4372.dtsi | 11 ++- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/dra7.dtsi | 12 ++- arch/arm/boot/dts/dra72x.dtsi | 2 +- arch/arm/boot/dts/dra74x.dtsi | 2 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 ++++- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 +++--- arch/arm/mach-omap2/omap-wakeupgen.c | 128 +++++++++++++++++++++++------- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 23 +++--- 18 files changed, 171 insertions(+), 78 deletions(-)
arch/arm/boot/dts/am4372.dtsi +10 -1
@@ -15,7 +15,7 @@ / { compatible = "ti,am4372", "ti,am43"; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; aliases {
@@ -48,6 +48,15 @@ #interrupt-cells = <3>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller at 48281000 { + compatible = "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; }; l2-cache-controller at 48242000 {
arch/arm/boot/dts/am437x-gp-evm.dts +0 -1
@@ -352,7 +352,6 @@ reg = <0x24>; compatible = "ti,tps65218"; interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ - interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <2>;
arch/arm/boot/dts/am437x-sk-evm.dts +0 -1
@@ -392,7 +392,6 @@ tps at 24 { compatible = "ti,tps65218"; reg = <0x24>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>;
arch/arm/boot/dts/am43x-epos-evm.dts +0 -1
@@ -369,7 +369,6 @@ reg = <0x24>; compatible = "ti,tps65218"; interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ - interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <2>;
arch/arm/boot/dts/dra7.dtsi +10 -2
@@ -64,6 +64,14 @@ interrupt-parent = <&gic>; }; + wakeupgen: interrupt-controller at 48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself.
@@ -92,7 +100,7 @@ reg = <0x44000000 0x1000000>, <0x45000000 0x1000>; interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; prm: prm at 4ae06000 { compatible = "ti,dra7-prm";
@@ -1341,7 +1349,7 @@ compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; interrupt-controller; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; #interrupt-cells = <3>; ti,max-irqs = <160>; ti,max-crossbar-sources = <MAX_SOURCES>;
arch/arm/boot/dts/dra72x.dtsi +1 -1
@@ -25,7 +25,7 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; }; };
arch/arm/boot/dts/dra74x.dtsi +1 -1
@@ -41,7 +41,7 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; };
arch/arm/boot/dts/omap4-duovero.dtsi +0 -2
@@ -173,14 +173,12 @@ twl: twl at 48 { reg = <0x48>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; }; twl6040: twl at 4b { compatible = "ti,twl6040"; reg = <0x4b>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ vio-supply = <&v1v8>;
arch/arm/boot/dts/omap4-panda-common.dtsi +3 -5
@@ -372,7 +372,6 @@ reg = <0x48>; /* IRQ# = 7 */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; }; twl6040: twl at 4b {
@@ -384,7 +383,6 @@ /* IRQ# = 119 */ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ vio-supply = <&v1v8>;
@@ -479,17 +477,17 @@ }; &uart2 { - interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART2_RX>; }; &uart3 { - interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART3_RX>; }; &uart4 { - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART4_RX>; };
arch/arm/boot/dts/omap4-sdp.dts +3 -5
@@ -363,7 +363,6 @@ reg = <0x48>; /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; }; twl6040: twl at 4b {
@@ -375,7 +374,6 @@ /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ vio-supply = <&v1v8>;
@@ -570,21 +568,21 @@ }; &uart2 { - interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART2_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { - interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart4 { - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART4_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>;
arch/arm/boot/dts/omap4-var-som-om44.dtsi +0 -2
@@ -185,7 +185,6 @@ reg = <0x48>; /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; }; twl6040: twl at 4b {
@@ -197,7 +196,6 @@ /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */ vio-supply = <&v1v8>;
arch/arm/boot/dts/omap4.dtsi +14 -4
@@ -14,7 +14,7 @@ / { compatible = "ti,omap4430", "ti,omap4"; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; aliases { i2c0 = &i2c1;
@@ -56,6 +56,7 @@ #interrupt-cells = <3>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; + interrupt-parent = <&gic>; }; L2: l2-cache-controller at 48242000 {
@@ -70,6 +71,15 @@ clocks = <&mpu_periphclk>; reg = <0x48240600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller at 48281000 { + compatible = "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; }; /*
@@ -319,7 +329,7 @@ uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; };
@@ -327,7 +337,7 @@ uart3: serial at 48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; };
@@ -335,7 +345,7 @@ uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; };
arch/arm/boot/dts/omap5-cm-t54.dts +0 -1
@@ -412,7 +412,6 @@ palmas: palmas at 48 { compatible = "ti,palmas"; interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-parent = <&gic>; reg = <0x48>; interrupt-controller; #interrupt-cells = <2>;
arch/arm/boot/dts/omap5-uevm.dts +0 -2
@@ -311,7 +311,6 @@ palmas: palmas at 48 { compatible = "ti,palmas"; interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-parent = <&gic>; reg = <0x48>; interrupt-controller; #interrupt-cells = <2>;
@@ -521,7 +520,6 @@ pinctrl-0 = <&twl6040_pins>; interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */ vio-supply = <&smps7_reg>;
arch/arm/boot/dts/omap5.dtsi +17 -9
@@ -18,7 +18,7 @@ #size-cells = <1>; compatible = "ti,omap5"; - interrupt-parent = <&gic>; + interrupt-parent = <&wakeupgen>; aliases { i2c0 = &i2c1;
@@ -79,6 +79,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; }; pmu {
@@ -95,6 +96,15 @@ <0x48212000 0x1000>, <0x48214000 0x2000>, <0x48216000 0x2000>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller at 48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; }; /*
@@ -458,7 +468,7 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; };
@@ -466,7 +476,7 @@ uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; };
@@ -474,7 +484,7 @@ uart3: serial at 48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; };
@@ -482,7 +492,7 @@ uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; };
@@ -490,7 +500,7 @@ uart5: serial at 48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; };
@@ -498,7 +508,7 @@ uart6: serial at 48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; };
@@ -883,14 +893,12 @@ usbhsohci: ohci at 4a064800 { compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; }; usbhsehci: ehci at 4a064c00 { compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; };
arch/arm/mach-omap2/omap-wakeupgen.c +98 -30
195 lines not on this page · raw message
arch/arm/mach-omap2/omap-wakeupgen.h +0 -1
@@ -33,7 +33,6 @@#define OMAP_TIMESTAMPCYCLELO 0xc08#define OMAP_TIMESTAMPCYCLEHI 0xc0c -extern int __init omap_wakeupgen_init (void );extern void __iomem *omap_get_wakeupgen_base (void );extern int omap_secure_apis_support (void );#endif
arch/arm/mach-omap2/omap4-common.c +14 -9
@@ -241,26 +241,26 @@ static int __init omap4_sar_ram_init(void) }omap_early_initcall (omap4_sar_ram_init); -static const struct of_device_id gic_match[] = { - { .compatible ="arm,cortex-a9-gic" , }, - { .compatible ="arm,cortex-a15-gic" , }, +static const struct of_device_id intc_match[] = { + { .compatible ="ti,omap4-wugen-mpu" , }, + { .compatible ="ti,omap5-wugen-mpu" , }, { }, }; -static struct device_node *gic_node; +static struct device_node *intc_node;unsigned int omap4_xlate_irq (unsigned int hwirq) {struct of_phandle_args irq_data;unsigned int irq; -if (!gic_node) - gic_node =of_find_matching_node (NULL , gic_match); +if (!intc_node) + intc_node =of_find_matching_node (NULL , intc_match); -if (WARN_ON (!gic_node)) +if (WARN_ON (!intc_node))return hwirq; - irq_data.np = gic_node; + irq_data.np = intc_node; irq_data.args_count =3 ; irq_data.args[0 ] =0 ; irq_data.args[1 ] = hwirq -OMAP44XX_IRQ_GIC_START ;
@@ -277,6 +277,12 @@ void __init omap_gic_of_init(void) {struct device_node *np; + intc_node =of_find_matching_node (NULL , intc_match); +if (WARN_ON (!intc_node)) { +pr_err ("No WUGEN found in DT, system will misbehave.\n" ); +pr_err ("UPDATE YOUR DEVICE TREE!\n" ); + } +/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ if (!cpu_is_omap446x ()) goto skip_errata_init;
@@ -290,6 +296,5 @@ void __init omap_gic_of_init(void)WARN_ON (!twd_base); skip_errata_init: -omap_wakeupgen_init ();irqchip_init (); }
Signature · 1 line
2.1.4
Tony Lindgren
maintainerv6 cover irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
In reply to Marc ZyngierQuoted 7 lines · Marc Zyngier
This series is extracted from [4], which is trying to remove all traces of
gic_arch_extnfrom the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
...
Quoted 26 lines
Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++---------
Quoted 8 lines
drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.h
For merging this, how about Marc sets up an immutable branch against v4.0-rc1 that both Jason and I can merge it in? Then Jason can send the pull request I can sort out the merge conflict issues.
Regards,
Tony
v6 cover irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
Hey Tony,
Quoted 44 lines · Tony Lindgren
Quoted 7 lines · Marc Zyngier
This series is extracted from [4], which is trying to remove all traces of
gic_arch_extnfrom the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
...
Quoted 26 lines
Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++---------Quoted 8 lines
drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.h
Quoted 3 lines
For merging this, how about Marc sets up an immutable branch against v4.0-rc1 that both Jason and I can merge it in? Then Jason can send the pull request I can sort out the merge conflict issues.
If you don't mind, I'll create the branch. I tend to fixup some nitpicks when I apply patches for irqchip. If there are any nits you'd like me to fix while I'm applying, just let me know.
thx,
Jason.
Tony Lindgren
maintainerv6 cover irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
Quoted 47 lines · Jason Cooper
Hey Tony,
Quoted 44 lines · Tony Lindgren
Quoted 7 lines · Marc Zyngier
This series is extracted from [4], which is trying to remove all traces of
gic_arch_extnfrom the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
...
Quoted 34 lines
Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++--------- drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.h
Quoted 7 lines
Quoted 3 lines
For merging this, how about Marc sets up an immutable branch against v4.0-rc1 that both Jason and I can merge it in? Then Jason can send the pull request I can sort out the merge conflict issues.
If you don't mind, I'll create the branch. I tend to fixup some nitpicks when I apply patches for irqchip. If there are any nits you'd like me to fix while I'm applying, just let me know.
That works for me thanks as long as it works for Marc.
Regards,
Tony
v6 cover irqchip: Move OMAP{4, 5}/DRA7 to use stacked domains
Quoted 52 lines · Tony Lindgren
Quoted 51 lines · Jason Cooper
Hey Tony,
Quoted 47 lines · Tony Lindgren
Quoted 7 lines · Marc Zyngier
This series is extracted from [4], which is trying to remove all traces of
gic_arch_extnfrom the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
...
Quoted 26 lines
Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++---------Quoted 8 lines
drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.hFor merging this, how about Marc sets up an immutable branch against v4.0-rc1 that both Jason and I can merge it in? Then Jason can send the pull request I can sort out the merge conflict issues.
Quoted 5 lines
Quoted 3 lines
If you don't mind, I'll create the branch. I tend to fixup some nitpicks when I apply patches for irqchip. If there are any nits you'd like me to fix while I'm applying, just let me know.
That works for me thanks as long as it works for Marc.
Definitely works for me. I just want to get rid of these patches! ;-)
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Jason Cooper
Appliedv6 cover irqchip: Move OMAP{4,5}/DRA7 to use stacked domains
In reply to Marc ZyngierMarc,
Quoted 83 lines · Marc Zyngier
This series is extracted from [4], which is trying to remove all traces of
gic_arch_extnfrom the tree. As some maintainers are more responsive than others (understatement of the year...), I've decided to split it per sub-arch, and get it moving, at least partially.This series addresses OMAP{4,5} by converting the WUGEN to stacked domains. The DRA7 crossbar gets the same treatment.
It is worth realizing that:
- I haven't been able to test this as much as I would have wanted to (it's only been tested on omap4 and omap5).
- This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees...
Based on 4.0-rc1.
* From v5: [5]
- Allow interrupt affinity to be changed* From v4: [4]
- Extracted from the full series
- Rebased on 4.0-rc1* From v3 [3]:
- Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
- Fixed more iMX6 DTs (Stephan)
- Fixed Exynos4/5 DTs* From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan* From v1 [1]:
- Rebased on 3.19-rc3
- Fixed a number of additional platforms
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth[5]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325178.html
[4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html
[3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
[2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
[1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.htmlMarc Zyngier (7):
genirq: Addirqchip_set_wake_parent
irqchip: crossbar: convert dra7 crossbar to stacked domains
DT: update ti,irq-crossbar binding
irqchip: GIC: get rid of routable domain
DT: arm,gic: kill arm,routable-irqs
DT: omap4/5: add binding for the wake-up generator
ARM: omap: convert wakeupgen to stacked domainsDocumentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../interrupt-controller/ti,omap4-wugen-mpu | 33 ++++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/am437x-gp-evm.dts | 1 - arch/arm/boot/dts/am437x-sk-evm.dts | 1 - arch/arm/boot/dts/am43x-epos-evm.dts | 1 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 43 +++-- arch/arm/boot/dts/dra72-evm.dts | 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/omap4-duovero.dtsi | 2 - arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +- arch/arm/boot/dts/omap4-sdp.dts | 8 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 - arch/arm/boot/dts/omap4.dtsi | 18 +- arch/arm/boot/dts/omap5-cm-t54.dts | 1 - arch/arm/boot/dts/omap5-uevm.dts | 2 - arch/arm/boot/dts/omap5.dtsi | 26 ++- arch/arm/mach-omap2/omap-wakeupgen.c | 128 ++++++++++--- arch/arm/mach-omap2/omap-wakeupgen.h | 1 - arch/arm/mach-omap2/omap4-common.c | 27 +-- drivers/irqchip/irq-crossbar.c | 210 ++++++++++++---------
Quoted 8 lines
drivers/irqchip/irq-gic.c | 59 +----- include/linux/irq.h | 1 + include/linux/irqchip/arm-gic.h | 6 - include/linux/irqchip/irq-crossbar.h | 11 -- kernel/irq/chip.c | 16 ++ 30 files changed, 376 insertions(+), 278 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu delete mode 100644 include/linux/irqchip/irq-crossbar.h
Applied to irqchip/stacked-omap.
thx,
Jason.