Support for Fujitsu MB86S7X SoCs

From: Jassi Brar <[email protected]>

Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.

Signed-off-by Jassi Brar <[email protected]>

Signed-off-by Andy Green <[email protected]>

Signed-off-by Vincent Yang <[email protected]>

Signed-off-by Tetsuya Nuriya <[email protected]>

---
  .../devicetree/bindings/mailbox/arm-mhu.txt        |  43 +++++
  drivers/mailbox/Kconfig                            |   9 +
  drivers/mailbox/Makefile                           |   2 +
  drivers/mailbox/arm_mhu.c                          | 195 +++++++++++++++++++++
  4 files changed, 249 insertions(+)

create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt create mode 100644 drivers/mailbox/arm_mhu.c

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +0 -0

new file mode 100644
index 0000000..4971f03

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +19 -0

+Example:
+--------
+
+	mhu: mailbox at 2b1f0000 {
+		#mbox-cells = <1>;
+		compatible = "arm,mhu", "arm,primecell";
+		reg = <0 0x2b1f0000 0x1000>;
+		interrupts = <0 36 4>, /* LP-NonSecure */
+			     <0 35 4>, /* HP-NonSecure */
+			     <0 37 4>; /* Secure */
+		clocks = <&clock 0 2 1>;
+		clock-names = "apb_pclk";
+	};
+
+	mhu_client: scb at 2e000000 {
+		compatible = "fujitsu,mb86s70-scb-1.0";
+		reg = <0 0x2e000000 0x4000>;
+		mboxes = <&mhu 1>; /* HP-NonSecure */
+	};

drivers/mailbox/arm_mhu.c new file +27 -0

new file mode 100644
index 0000000..ac693c6
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar <[email protected]>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/amba/bus.h>
+#include <linux/mailbox_controller.h>
+
+#define INTR_STAT_OFS	0x0

drivers/mailbox/arm_mhu.c new file +22 -0

+static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
+{
+	int i, err;
+	struct arm_mhu *mhu;
+	struct device *dev = &adev->dev;
+	int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
+
+	/* Allocate memory for device */
+	mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
+	if (!mhu)
+		return -ENOMEM;
+
+	mhu->base = devm_ioremap_resource(dev, &adev->res);
+	if (IS_ERR(mhu->base)) {
+		dev_err(dev, "ioremap failed\n");
+		return PTR_ERR(mhu->base);
+	}
+
+	for (i = 0; i < MHU_CHANS; i++) {
+		mhu->chan[i].con_priv = &mhu->mlink[i];
+		mhu->mlink[i].irq = adev->irq[i];
+		mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];

Hi Vincent,

I see that this driver is queued but most of my earlier comments were not addressed.

*No ACK from DT binding maintainers too*.

Quoted 5 lines

+++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +3 -0

@@ -0,0 +1,43 @@
+ARM MHU Mailbox Driver
+======================
+

Documentation/devicetree/bindings/mailbox/arm-mhu.txt line 6

Quoted 3 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +3 -0

+The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
+3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any

As I had mentioned before it's just one implementation, the IP had provision bi-directional interrupts and the binding *has to consider* that instead of having to workaround that later.

Documentation/devicetree/bindings/mailbox/arm-mhu.txt line 11

Quoted 2 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +2 -0

+The last channel is specified to be a 'Secure' resource, hence can't be
+used by Linux running NS.

Correct so drop the support for secure channel until the first user comes up.

I am worried it might generate abort if someone tries to access it in ARM64 which always runs in non-secure.

drivers/mailbox/arm_mhu.c line 176

Quoted 4 lines

drivers/mailbox/arm_mhu.c new file +4 -0

+
+static struct amba_id mhu_ids[] = {
+       {
+               .id     = 0x1bb098,

As I mentioned couple of times this is broken. Please refer my earlier mail for details. You are skipping a field to compare which incorrect. You are just trying to get it working with existing AMBA driver without any changes matching the IDs partially.

Quoted 5 lines · Sudeep Holla

Hi Vincent,

I see that this driver is queued but most of my earlier comments were not addressed.

Some of your comments have been addressed as changes and some as replies.

Quoted 2 lines

*No ACK from DT binding maintainers too*.

Yeah it would have been great to have some ack. It has been many months now, but I see its not uncommon for bindings go in via maintainers. I assume folks find it just normal.

Quoted 5 lines

Quoted 5 lines

+++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +3 -0

@@ -0,0 +1,43 @@
+ARM MHU Mailbox Driver
+======================
+

Quoted 9 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt line 6

Quoted 3 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +3 -0

+The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
+3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any

As I had mentioned before it's just one implementation, the IP had provision bi-directional interrupts and the binding *has to consider* that instead of having to workaround that later.

I will reply in yet another way.... the spec I have don't mention that (and it makes sense) and your platform doesn't do that either. I would have had to do something about it, had there been such a weird setup, but there's none known.

So let us please avoid getting into bikeshedding discussion yet
again. Otherwise almost every binding is broken because there could always be some platform that does weird things with irqs.

Quoted 6 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt line 11

Quoted 2 lines

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +2 -0

+The last channel is specified to be a 'Secure' resource, hence can't be
+used by Linux running NS.

Correct so drop the support for secure channel until the first user comes up.

In your last post you said:
"Sorry my statement was not clear, I wanted to ask you to add that info
to the binding."
Not that it makes sense to say the obvious, I added it just to
address your comment.

Quoted 3 lines

I am worried it might generate abort if someone tries to access it in ARM64 which always runs in non-secure.

Abort should have happened years ago if someone _tries_ to access a secure resource from non-secure mode ;)
How do you protect such people from "trying to" dereference NULL pointers? (you made me repeat Nth time).

Quoted 11 lines

drivers/mailbox/arm_mhu.c line 176

Quoted 4 lines

drivers/mailbox/arm_mhu.c new file +4 -0

+
+static struct amba_id mhu_ids[] = {
+       {
+               .id     = 0x1bb098,

As I mentioned couple of times this is broken. Please refer my earlier mail for details. You are skipping a field to compare which incorrect. You are just trying to get it working with existing AMBA driver without any changes matching the IDs partially.

I did not miss your last mail. Let me try to reply in even simpler terms... PID[0,3] identification is fine grained enough. If/when we have some platform with non-ARM MHU, we could catch that in this driver. Most likely even then the reg-map won't change drastically, if at all. So we could ignore the PID4, otherwise we check PID4 in this driver and adapt the behavior.

From: Jassi Brar <[email protected]>

Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.

Signed-off-by Jassi Brar <[email protected]>

Signed-off-by Andy Green <[email protected]>

Signed-off-by Vincent Yang <[email protected]>

Signed-off-by Tetsuya Nuriya <[email protected]>

---
  .../devicetree/bindings/mailbox/arm-mhu.txt        |  43 +++++
  drivers/mailbox/Kconfig                            |   9 +
  drivers/mailbox/Makefile                           |   2 +
  drivers/mailbox/arm_mhu.c                          | 195 +++++++++++++++++++++
  4 files changed, 249 insertions(+)

create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt create mode 100644 drivers/mailbox/arm_mhu.c

drivers/mailbox/arm_mhu.c new file +6 -0

+	writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+	return 0;
+}
+
+static int mhu_startup(struct mbox_chan *chan)

drivers/mailbox/arm_mhu.c line 79

Quoted 5 lines

drivers/mailbox/arm_mhu.c new file +4 -0

+static int mhu_send_data(struct mbox_chan *chan, void *data)
+{
+       struct mhu_link *mlink = chan->con_priv;
+       u32 *arg = data;

Arnd doesn't like this and had suggestions in some other thread.

Quoted 13 lines

drivers/mailbox/arm_mhu.c new file +13 -0

+       writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+       return 0;
+}
+
+static int mhu_startup(struct mbox_chan *chan)
+{
+       struct mhu_link *mlink = chan->con_priv;
+       u32 val;
+       int ret;
+
+       val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+       writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);

drivers/mailbox/arm_mhu.c line 96

Quoted 3 lines

drivers/mailbox/arm_mhu.c new file +3 -0

+
+       ret = request_irq(mlink->irq, mhu_rx_interrupt,
+                         IRQF_SHARED, "mhu_link", chan);

Any reason we can't move this to probe and have {en,dis}able_irq here if needed. I has seen it was too heavy to have these especially when sending small packets.

Quoted 8 lines · Sudeep Holla

drivers/mailbox/arm_mhu.c line 79

Quoted 5 lines

drivers/mailbox/arm_mhu.c new file +4 -0

+static int mhu_send_data(struct mbox_chan *chan, void *data)
+{
+       struct mhu_link *mlink = chan->con_priv;
+       u32 *arg = data;

Arnd doesn't like this and had suggestions in some other thread.

No, Arnd suggested doing it this way. And another platform's driver was made to do this way.

Quoted 13 lines

Quoted 13 lines

drivers/mailbox/arm_mhu.c new file +13 -0

+       writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+       return 0;
+}
+
+static int mhu_startup(struct mbox_chan *chan)
+{
+       struct mhu_link *mlink = chan->con_priv;
+       u32 val;
+       int ret;
+
+       val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+       writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);

Quoted 9 lines

drivers/mailbox/arm_mhu.c line 96

Quoted 3 lines

drivers/mailbox/arm_mhu.c new file +3 -0

+
+       ret = request_irq(mlink->irq, mhu_rx_interrupt,
+                         IRQF_SHARED, "mhu_link", chan);

Any reason we can't move this to probe and have {en,dis}able_irq here if needed. I has seen it was too heavy to have these especially when sending small packets.

I see you used to do memcpy in irq-handler
https://git.linaro.org/landing-teams/working/arm/kernel.git/blob/HEAD:/drivers/mailbox/arm_mhu.c
perhaps you were using your old driver?

If you use this new driver, and send packets so often that request-release irq has effect, maybe should hold the mailbox reference for lifetime. I remember suggesting you that already and I remember you said that's how it was.

From: Jassi Brar <[email protected]>

Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.

Signed-off-by Jassi Brar <[email protected]>

Signed-off-by Andy Green <[email protected]>

Signed-off-by Vincent Yang <[email protected]>

Signed-off-by Tetsuya Nuriya <[email protected]>

---
  .../devicetree/bindings/mailbox/arm-mhu.txt        |  43 +++++
  drivers/mailbox/Kconfig                            |   9 +
  drivers/mailbox/Makefile                           |   2 +
  drivers/mailbox/arm_mhu.c                          | 195 +++++++++++++++++++++
  4 files changed, 249 insertions(+)

create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt create mode 100644 drivers/mailbox/arm_mhu.c

Documentation/devicetree/bindings/mailbox/arm-mhu.txt new file +14 -0

new file mode 100644
index 0000000..4971f03
@@ -0,0 +1,43 @@
+ARM MHU Mailbox Driver
+======================
+
+The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
+3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any
+received data. However, there is no specified way of knowing if the sent
+data has been read by the remote. This driver assumes the sender polls
+STAT register and the remote clears it after having read the data.
+The last channel is specified to be a 'Secure' resource, hence can't be
+used by Linux running NS.
+
+Mailbox Device Node:
+====================

I tried using this driver and found that AMBA driver expects apb_clk without which probe fails. Though your example have it, it's not explicit from the binding. Also AMBA binding expects the primecell id in the binding.

Quoted 4 lines · Sudeep Holla

I tried using this driver and found that AMBA driver expects apb_clk without which probe fails. Though your example have it, it's not explicit from the binding. Also AMBA binding expects the primecell id in the binding.

That's optional:

Optional properties:

- arm,primecell-periphid : Value to override the h/w value with

It's only required when the hardware doesn't provide the correct value.

From: Jassi Brar <[email protected]>

The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.

Signed-off-by Andy Green <[email protected]>

Signed-off-by Vincent Yang <[email protected]>

Signed-off-by Tetsuya Nuriya <[email protected]>

---
 .../bindings/clock/fujitsu,mb86s70-crg11.txt       |  26 ++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-mb86s7x.c                          | 386 +++++++++++++++++++++
 3 files changed, 413 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
 create mode 100644 drivers/clk/clk-mb86s7x.c

Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt new file +26 -0

new file mode 100644
index 0000000..3323962
@@ -0,0 +1,26 @@
+Fujitsu CRG11 clock driver bindings
+-----------------------------------
+
+Required properties :
+- compatible : Shall contain "fujitsu,mb86s70-crg11"
+- #clock-cells : Shall be 3 {cntrlr domain port}
+
+The consumer specifies the desired clock pointing to its phandle.
+
+Example:
+
+       clock: crg11 {
+               compatible = "fujitsu,mb86s70-crg11";
+               #clock-cells = <3>;
+       };
+
+       mhu: mhu0 at 2b1f0000 {
+               #mbox-cells = <1>;
+               compatible = "arm,mhu";
+               reg = <0 0x2B1F0000 0x1000>;
+               interrupts = <0 36 4>, /* LP Non-Sec */
+                            <0 35 4>, /* HP Non-Sec */
+                            <0 37 4>; /* Secure */
+               clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
+               clock-names = "clk";
+       };

drivers/clk/Makefile +1 -0

index d478ceb..1d35f3b 100644
@@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1)          += clk-ls1x.o
 obj-$(CONFIG_COMMON_CLK_MAX_GEN)       += clk-max-gen.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)      += clk-max77686.o
 obj-$(CONFIG_COMMON_CLK_MAX77802)      += clk-max77802.o
+obj-$(CONFIG_ARCH_MB86S7X)             += clk-mb86s7x.o
 obj-$(CONFIG_ARCH_MOXART)              += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)             += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)              += clk-nspire.o

drivers/clk/clk-mb86s7x.c new file +386 -0

new file mode 100644
index 0000000..f39c25a
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/topology.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+
+#include <soc/mb86s7x/scb_mhu.h>
+
+#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
+#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
+
+struct mb86s7x_peri_clk {
+       u32 payload_size;
+       u32 cntrlr;
+       u32 domain;
+       u32 port;
+       u32 en;
+       u64 frequency;
+} __packed __aligned(4);
+
+struct hack_rate {
+       unsigned clk_id;
+       unsigned long rate;
+       int gated;
+};
+
+struct crg_clk {
+       struct clk_hw hw;
+       u8 cntrlr, domain, port;
+};
+
+static int crg_gate_control(struct clk_hw *hw, int en)
+{
+       struct crg_clk *crgclk = to_crg_clk(hw);
+       struct mb86s7x_peri_clk cmd;
+       int ret;
+
+       cmd.payload_size = sizeof(cmd);
+       cmd.cntrlr = crgclk->cntrlr;
+       cmd.domain = crgclk->domain;
+       cmd.port = crgclk->port;
+       cmd.en = en;
+
+       /* Port is UngatedCLK */
+       if (cmd.port == 8)
+               return en ? 0 : -EINVAL;
+
+       pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+                __func__, __LINE__, cmd.cntrlr,
+                cmd.domain, cmd.port, cmd.en);
+
+       ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
+                                 &cmd, sizeof(cmd));
+       if (ret < 0) {
+               pr_err("%s:%d failed!\n", __func__, __LINE__);
+               return ret;
+       }
+
+       pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+                __func__, __LINE__, cmd.cntrlr,
+                cmd.domain, cmd.port, cmd.en);
+
+       /* If the request was rejected */
+       if (cmd.en != en)
+               ret = -EINVAL;
+       else
+               ret = 0;
+
+       return ret;
+}
+
+static int crg_port_prepare(struct clk_hw *hw)
+{
+       return crg_gate_control(hw, 1);
+}
+
+static void crg_port_unprepare(struct clk_hw *hw)
+{
+       crg_gate_control(hw, 0);
+}
+
+static int
+crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
+{
+       struct crg_clk *crgclk = to_crg_clk(hw);
+       struct mb86s7x_peri_clk cmd;
+       int code, ret;
+
+       cmd.payload_size = sizeof(cmd);
+       cmd.cntrlr = crgclk->cntrlr;
+       cmd.domain = crgclk->domain;
+       cmd.port = crgclk->port;
+       cmd.frequency = *rate;
+
+       if (set) {
+               code = CMD_PERI_CLOCK_RATE_SET_REQ;
+               pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+                        __func__, __LINE__, cmd.cntrlr,
+                        cmd.domain, cmd.port, cmd.frequency);
+       } else {
+               code = CMD_PERI_CLOCK_RATE_GET_REQ;
+               pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
+                        __func__, __LINE__, cmd.cntrlr,
+                        cmd.domain, cmd.port);
+       }
+
+       ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+       if (ret < 0) {
+               pr_err("%s:%d failed!\n", __func__, __LINE__);
+               return ret;
+       }
+
+       if (set)
+               pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+                        __func__, __LINE__, cmd.cntrlr,
+                        cmd.domain, cmd.port, cmd.frequency);
+       else
+               pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
+                        __func__, __LINE__, cmd.cntrlr,
+                        cmd.domain, cmd.port, cmd.frequency);
+
+       *rate = cmd.frequency;
+       return 0;
+}
+
+static unsigned long
+crg_port_recalc_rate(struct clk_hw *hw,        unsigned long parent_rate)
+{
+       unsigned long rate;
+
+       crg_rate_control(hw, 0, &rate);
+
+       return rate;
+}
+
+static long
+crg_port_round_rate(struct clk_hw *hw,
+                   unsigned long rate, unsigned long *pr)
+{
+       return rate;
+}
+
+static int
+crg_port_set_rate(struct clk_hw *hw,
+                 unsigned long rate, unsigned long parent_rate)
+{
+       return crg_rate_control(hw, 1, &rate);
+}
+
+const struct clk_ops crg_port_ops = {
+       .prepare = crg_port_prepare,
+       .unprepare = crg_port_unprepare,
+       .recalc_rate = crg_port_recalc_rate,
+       .round_rate = crg_port_round_rate,
+       .set_rate = crg_port_set_rate,
+};
+
+struct mb86s70_crg11 {
+       struct mutex lock; /* protects CLK populating and searching */
+};
+
+static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
+{
+       struct mb86s70_crg11 *crg11 = data;
+       struct clk_init_data init;
+       u32 cntrlr, domain, port;
+       struct crg_clk *crgclk;
+       struct clk *clk;
+       char clkp[20];
+
+       if (clkspec->args_count != 3)
+               return ERR_PTR(-EINVAL);
+
+       cntrlr = clkspec->args[0];
+       domain = clkspec->args[1];
+       port = clkspec->args[2];
+
+       if (port > 7)
+               snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
+       else
+               snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
+
+       mutex_lock(&crg11->lock);
+
+       clk = __clk_lookup(clkp);
+       if (clk) {
+               mutex_unlock(&crg11->lock);
+               return clk;
+       }
+
+       crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
+       if (!crgclk) {
+               mutex_unlock(&crg11->lock);
+               return ERR_PTR(-ENOMEM);
+       }
+
+       init.name = clkp;
+       init.num_parents = 0;
+       init.ops = &crg_port_ops;
+       init.flags = CLK_IS_ROOT;
+       crgclk->hw.init = &init;
+       crgclk->cntrlr = cntrlr;
+       crgclk->domain = domain;
+       crgclk->port = port;
+       clk = clk_register(NULL, &crgclk->hw);
+       if (IS_ERR(clk))
+               pr_err("%s:%d Error!\n", __func__, __LINE__);
+       else
+               pr_debug("Registered %s\n", clkp);
+
+       clk_register_clkdev(clk, clkp, NULL);
+       mutex_unlock(&crg11->lock);
+       return clk;
+}
+
+static void __init crg_port_init(struct device_node *node)
+{
+       struct mb86s70_crg11 *crg11;
+
+       crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
+       if (!crg11)
+               return;
+
+       mutex_init(&crg11->lock);
+
+       of_clk_add_provider(node, crg11_get, crg11);
+}
+CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
+
+struct cl_clk {
+       struct clk_hw hw;
+       int cluster;
+};
+
+struct mb86s7x_cpu_freq {
+       u32 payload_size;
+       u32 cluster_class;
+       u32 cluster_id;
+       u32 cpu_id;
+       u64 frequency;
+};
+
+static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
+{
+       struct cl_clk *clc = to_clc_clk(hw);
+       struct mb86s7x_cpu_freq cmd;
+       int code, ret;
+
+       cmd.payload_size = sizeof(cmd);
+       cmd.cluster_class = 0;
+       cmd.cluster_id = clc->cluster;
+       cmd.cpu_id = 0;
+       cmd.frequency = *rate;
+
+       if (get)
+               code = CMD_CPU_CLOCK_RATE_GET_REQ;
+       else
+               code = CMD_CPU_CLOCK_RATE_SET_REQ;
+
+       pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+                __func__, __LINE__, cmd.cluster_class,
+                cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+       ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+       if (ret < 0) {
+               pr_err("%s:%d failed!\n", __func__, __LINE__);
+               return;
+       }
+
+       pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+                __func__, __LINE__, cmd.cluster_class,
+                cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+       *rate = cmd.frequency;
+}
+
+static unsigned long
+clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
+{
+       unsigned long rate;
+
+       mhu_cluster_rate(hw, &rate, 1);
+       return rate;
+}
+
+static long
+clc_round_rate(struct clk_hw *hw, unsigned long rate,
+              unsigned long *unused)
+{
+       return rate;
+}
+
+static int
+clc_set_rate(struct clk_hw *hw, unsigned long rate,
+            unsigned long unused)
+{
+       unsigned long res = rate;
+
+       mhu_cluster_rate(hw, &res, 0);
+
+       return (res == rate) ? 0 : -EINVAL;
+}
+
+static struct clk_ops clk_clc_ops = {
+       .recalc_rate = clc_recalc_rate,
+       .round_rate = clc_round_rate,
+       .set_rate = clc_set_rate,
+};
+
+struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
+{
+       struct clk_init_data init;
+       struct cl_clk *clc;
+
+       clc = kzalloc(sizeof(*clc), GFP_KERNEL);
+       if (!clc)
+               return ERR_PTR(-ENOMEM);
+
+       clc->hw.init = &init;
+       clc->cluster = topology_physical_package_id(cpu_dev->id);
+
+       init.name = dev_name(cpu_dev);
+       init.ops = &clk_clc_ops;
+       init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
+       init.num_parents = 0;
+
+       return devm_clk_register(cpu_dev, &clc->hw);
+}
+
+static int mb86s7x_clclk_of_init(void)
+{
+       int cpu, ret = -ENODEV;
+       struct device_node *np;
+       struct clk *clk;
+
+       np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
+       if (!np || !of_device_is_available(np))
+               goto exit;
+
+       for_each_possible_cpu(cpu) {
+               struct device *cpu_dev = get_cpu_device(cpu);
+
+               if (!cpu_dev) {
+                       pr_err("failed to get cpu%d device\n", cpu);
+                       continue;
+               }
+
+               clk = mb86s7x_clclk_register(cpu_dev);
+               if (IS_ERR(clk)) {
+                       pr_err("failed to register cpu%d clock\n", cpu);
+                       continue;
+               }
+               if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
+                       pr_err("failed to register cpu%d clock lookup\n", cpu);
+                       continue;
+               }
+               pr_debug("registered clk for %s\n", dev_name(cpu_dev));
+       }
+       ret = 0;
+
+       platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
+exit:
+       of_node_put(np);
+       return ret;
+}
+module_init(mb86s7x_clclk_of_init);

Signature · 1 line

1.9.0