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ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

PATCH New Gregory CLEMENT 2 participants 4 messages Mar 17, 2015 – Mar 19, 2015 Device tree bindings

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Gregory CLEMENT

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#0 lore raw

PATCH 1/1 ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/arm/boot/dts/armada-370.dtsi | 1 +
 arch/arm/boot/dts/armada-xp.dtsi  | 1 +
 2 files changed, 2 insertions(+)
arch/arm/boot/dts/armada-370.dtsi +1 -0
index 27397f151def..b38bfa03d3bf 100644
@@ -129,6 +129,7 @@
 				compatible = "marvell,aurora-outer-cache";
 				reg = <0x08000 0x1000>;
 				cache-id-part = <0x100>;
+				cache-level = <2>;
 				cache-unified;
 				wt-override;
 			};
arch/arm/boot/dts/armada-xp.dtsi +1 -0
index 82917236a2fb..9806046dde1e 100644
@@ -78,6 +78,7 @@
 				compatible = "marvell,aurora-system-cache";
 				reg = <0x08000 0x1000>;
 				cache-id-part = <0x100>;
+				cache-level = <2>;
 				cache-unified;
 				wt-override;
 			};
Signature · 1 line
2.1.0
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#1 lore raw

PATCH 1/1 ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

Hi,

Quoted 3 lines · Gregory CLEMENT

For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree.

unless someone is against it, I will apply it on mvebu/dt tomorrow.

Thanks,

Gregory

Quoted 31 lines
Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/arm/boot/dts/armada-370.dtsi | 1 +
 arch/arm/boot/dts/armada-xp.dtsi  | 1 +
 2 files changed, 2 insertions(+)
arch/arm/boot/dts/armada-370.dtsi +1 -0
index 27397f151def..b38bfa03d3bf 100644
@@ -129,6 +129,7 @@
 				compatible = "marvell,aurora-outer-cache";
 				reg = <0x08000 0x1000>;
 				cache-id-part = <0x100>;
+				cache-level = <2>;
 				cache-unified;
 				wt-override;
 			};
arch/arm/boot/dts/armada-xp.dtsi +1 -0
index 82917236a2fb..9806046dde1e 100644
@@ -78,6 +78,7 @@
 				compatible = "marvell,aurora-system-cache";
 				reg = <0x08000 0x1000>;
 				cache-id-part = <0x100>;
+				cache-level = <2>;
 				cache-unified;
 				wt-override;
 			};
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#2 lore raw

PATCH 1/1 ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

In reply to Gregory CLEMENT

Dear Gregory CLEMENT,

Quoted 4 lines · Gregory CLEMENT

For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree.

Signed-off-by Gregory CLEMENT <[email protected]>
Reviewed-by Thomas Petazzoni <[email protected]>

Thanks,

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
author
#3 lore raw

PATCH 1/1 ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

Quoted 9 lines · Thomas Petazzoni

Dear Gregory CLEMENT,

Quoted 4 lines · Gregory CLEMENT

For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree.

Signed-off-by Gregory CLEMENT <[email protected]>
Reviewed-by Thomas Petazzoni <[email protected]>

applied on mvebu/dt with Thomas tag

Thanks,

Gregory

Quoted 5 lines

Thanks,

Thomas

Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com