armv8/fsl-lsch3: Add Freescale Debug Server driver

index 4997487..618fbc2 100644
@@ -10,6 +10,7 @@
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include "cpu.h"
 #include "mp.h"

@@ -384,7 +385,6 @@ int cpu_eth_init(bd_t *bis)
 	return error;
 }
 
-
 int arch_early_init_r(void)
 {
 	int rv;

index b140c1f..59d10bf 100644
@@ -30,6 +30,15 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL

@@ -88,7 +97,6 @@
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 
-
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
 

index 519d61c..a16c2c8 100644
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <libfdt.h>
+#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
 

@@ -79,6 +80,34 @@ void reset_cpu(ulong addr)
 {
 }
 
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	debug_server_init();
+#endif
+
+	return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+	unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+	dram_to_hide += mc_get_dram_block_size();
+#endif
+
+	return dram_to_hide;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	int error = 0;

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index 74b0085..76581cb 100644
@@ -9,6 +9,7 @@
 #include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_dpmng.h>
+#include <fsl_debug_server.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 static int mc_boot_status;

@@ -112,6 +113,9 @@ int mc_init(bd_t *bis)
 			gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
 	}
 
+#ifdef CONFIG_FSL_DEBUG_SERVER
+		mc_ram_addr -= debug_server_get_dram_block_size();
+#endif
 	/*
 	 * Management Complex cores should be held at reset out of POR.
 	 * U-boot should be the first software to touch MC. To be safe,

index f80efed..c70ba70 100644
@@ -19,6 +19,9 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
+/* We need architecture specific misc initializations */
+#define CONFIG_ARCH_MISC_INIT
+
 /* Link Definitions */
 #define CONFIG_SYS_TEXT_BASE		0x30001000
 

@@ -206,6 +209,14 @@
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 
+/* Debug Server firmware */
+#define CONFIG_FSL_DEBUG_SERVER
+#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR			0x580C00000ULL
+/* 2 sec timeout */
+#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
+
 /* MC firmware */
 #define CONFIG_FSL_MC_ENET
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)

@@ -217,9 +228,9 @@
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	(256 * 1024)
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
 
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_MEM_TOP_HIDE		mc_get_dram_block_size()
+/* Carve out a DDR region which will not be used by u-boot/Linux */
+#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
+#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
 #endif
 
 /* Command line configuration */

@@ -251,7 +262,6 @@
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
 
-
 #define CONFIG_NR_DRAM_BANKS		3
 
 #define CONFIG_HWCONFIG

@@ -298,7 +308,7 @@
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 
 #ifndef __ASSEMBLY__
-unsigned long mc_get_dram_block_size(void);
+unsigned long get_dram_size_to_hide(void);
 #endif
 
 #endif /* __LS2_COMMON_H */

index b9f089e..28d5961 100644
@@ -56,4 +56,5 @@ struct mc_ccsr_registers {
 int mc_init(bd_t *bis);
 
 int get_mc_boot_status(void);
+unsigned long mc_get_dram_block_size(void);
 #endif

new file mode 100644
index 0000000..28d8adb
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_DBG_SERVER_H__
+#define __FSL_DBG_SERVER_H__
+
+#include <asm/io.h>
+#include <common.h>
+
+/*
+ * Define Debug Server firmware version information
+ */
+
+/* Major version number: incremented on API compatibility changes */
+#define DEBUG_SERVER_VER_MAJOR	0
+
+/* Minor version number: incremented on API additions (backward
+ * compatible); reset when major version is incremented.
+ */
+#define DEBUG_SERVER_VER_MINOR	1
+
+#define DEBUG_SERVER_INIT_STATUS	(1 << 0)
+#define DEBUG_SERVER_INIT_STATUS_MASK	(0x00000001)
+
+int debug_server_init(void);
+unsigned long debug_server_get_dram_block_size(void);
+
+#endif /* __FSL_DBG_SERVER_H__ */
+

index 618fbc2..94fd147 100644
@@ -380,7 +380,7 @@ int cpu_eth_init(bd_t *bis)
 	int error = 0;
 
 #ifdef CONFIG_FSL_MC_ENET
-	error = mc_init(bis);
+	error = fsl_mc_ldpaa_init(bis);
 #endif
 	return error;
 }

index 59d10bf..0217582 100644
@@ -8,6 +8,8 @@
 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
 
 #include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_PAGE_SIZE		0x10000
 #define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
 /* Link Definitions */

index a16c2c8..e78c63a 100644
@@ -164,6 +164,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
+	fsl_mc_ldpaa_exit(bd);
 #endif
 
 	return 0;

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index c9fe021..33f84f3 100644
@@ -1,4 +1,4 @@
-/* Copyright 2014 Freescale Semiconductor Inc.
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,10 +7,6 @@
 
 /* Command IDs */
 #define DPMNG_CMDID_GET_VERSION			0x831
-#define DPMNG_CMDID_RESET_AIOP			0x832
-#define DPMNG_CMDID_LOAD_AIOP			0x833
-#define DPMNG_CMDID_RUN_AIOP			0x834
-#define DPMNG_CMDID_RESET_MC_PORTAL		0x835
 
 /*                cmd, param, offset, width, type, arg_name */
 #define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \

@@ -20,30 +16,4 @@ do { \
 	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, mc_ver_info->minor); \
 } while (0)
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
-	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \
-			    img_iova) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
-	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
-	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, img_size); \
-	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, img_iova); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    aiop_tile_id); \
-	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
-	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->cores_mask); \
-	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, cfg->options); \
-} while (0)
-
 #endif /* __FSL_DPMNG_CMD_H */

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index 7c8e003..3fc1f98 100644
@@ -1,7 +1,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
  * Author: German Rivera <[email protected]>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -32,7 +32,7 @@ int mc_send_command(struct fsl_mc_io *mc_io,
 		    struct mc_command *cmd)
 {
 	enum mc_cmd_status status;
-	int timeout = 2000;
+	int timeout = 6000;
 
 	mc_write_command(mc_io->mmio_regs, cmd);
 

@@ -52,7 +52,7 @@ int mc_send_command(struct fsl_mc_io *mc_io,
 	if (status != MC_CMD_STATUS_OK) {
 		printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
 		       mc_io->mmio_regs,
-		       (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header),
+			(unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header),
 		       (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
 		       (unsigned int)status);
 

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index 0217582..1d2a7fa 100644
@@ -10,6 +10,12 @@
 #include <fsl_ddrc_version.h>
 
 #define CONFIG_SYS_PAGE_SIZE		0x10000
+
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+#endif
+
 #define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
 /* Link Definitions */

index e29ee3d..2a2b0af 100644
@@ -397,9 +397,10 @@ int dpbp_init(struct dprc_obj_desc obj_desc)
 	return 0;
 }
 
-int dprc_init_container_obj(struct dprc_obj_desc obj_desc)
+int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
 {
-	int error = 0;
+	int error = 0, state = 0;
+	struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
 	if (!strcmp(obj_desc.type, "dpbp")) {
 		if (!dflt_dpbp) {
 			error = dpbp_init(obj_desc);

@@ -412,6 +413,15 @@ int dprc_init_container_obj(struct dprc_obj_desc obj_desc)
 			if (error < 0)
 				printf("dpio_init failed\n");
 		}
+	} else if (!strcmp(obj_desc.type, "dpni")) {
+		strcpy(dpni_endpoint.type, obj_desc.type);
+		dpni_endpoint.id = obj_desc.id;
+		error = dprc_get_connection(dflt_mc_io, dprc_handle,
+				     &dpni_endpoint, &dpmac_endpoint, &state);
+		if (!strcmp(dpmac_endpoint.type, "dpmac"))
+			error = ldpaa_eth_init(obj_desc);
+		if (error < 0)
+			printf("ldpaa_eth_init failed\n");
 	}
 
 	return error;

@@ -436,7 +446,7 @@ int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
 		debug("Discovered object: type %s, id %d, req %s\n",
 		      obj_desc.type, obj_desc.id, obj_type);
 
-		error = dprc_init_container_obj(obj_desc);
+		error = dprc_init_container_obj(obj_desc, dprc_handle);
 		if (error < 0) {
 			printf("dprc_init_container_obj(i=%d) failed: %d\n",
 			       i, error);

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index cf4b079..9f06978 100644
@@ -16,6 +16,7 @@
 
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dprc.h>
 #include <fsl-mc/fsl_dpbp.h>
 
 extern struct fsl_mc_io *dflt_mc_io;

@@ -45,4 +46,5 @@ struct fsl_dpio_obj {
 extern struct fsl_dpio_obj *dflt_dpio;
 
 int mc_init(void);
+int ldpaa_eth_init(struct dprc_obj_desc obj_desc);
 #endif /* _FSL_MC_PRIVATE_H_ */

index c70ba70..eb7b9b2 100644
@@ -78,7 +78,7 @@
 #define COUNTER_FREQUENCY		12000000	/* 12MHz */
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
 
 /* I2C */
 #define CONFIG_CMD_I2C

index 3902e9f..45d299c 100644
@@ -168,4 +168,13 @@ void init_final_memctl_regs(void)
 #ifdef CONFIG_SYS_CSPR0_FINAL
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
 #endif
+#ifdef CONFIG_SYS_CSPR1_FINAL
+	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#endif
+#ifdef CONFIG_SYS_CSPR3_FINAL
+	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#endif
 }

index b283eae..16266fa 100644
@@ -292,7 +292,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 	struct fsl_ifc *ifc = ctrl->regs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 	u32 time_start;
-	u32 eccstat[4] = {0};
+	u32 eccstat[8] = {0};
 	int i;
 
 	/* set the chip select for NAND Transaction */

@@ -325,8 +325,15 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 		int sector = bufnum * chip->ecc.steps;
 		int sector_end = sector + chip->ecc.steps - 1;
 
-		for (i = sector / 4; i <= sector_end / 4; i++)
+		for (i = sector / 4; i <= sector_end / 4; i++) {
+			if (i >= ARRAY_SIZE(eccstat)) {
+				printf("%s: eccstat too small for %d\n",
+				       __func__, i);
+				return -EIO;
+			}
+
 			eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
+		}
 
 		for (i = sector; i <= sector_end; i++) {
 			errors = check_read_ecc(mtd, ctrl, eccstat, i);

index fc5ee35..02a173e 100644
@@ -114,6 +114,9 @@ static u16 i2c_clk_div[50][2] = {
 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
 #endif
+#ifndef CONFIG_SYS_MXC_I2C4_SPEED
+#define CONFIG_SYS_MXC_I2C4_SPEED 100000
+#endif
 
 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 #define CONFIG_SYS_MXC_I2C1_SLAVE 0

@@ -124,6 +127,9 @@ static u16 i2c_clk_div[50][2] = {
 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
 #endif
+#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
+#define CONFIG_SYS_MXC_I2C4_SLAVE 0
+#endif
 
 
 /*

@@ -545,10 +551,18 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-	defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102XA) ||\
+	defined(CONFIG_LS2085A)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,
 			 CONFIG_SYS_MXC_I2C3_SPEED,
 			 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 #endif
+#ifdef CONFIG_LS2085A
+U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C4_SPEED,
+			 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
+#endif