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armv8/ls2085aqds: NAND boot support

PATCH Superseded York Sun 2 participants 4 messages Mar 24, 2015

Subsystems (4)
Arm (32-bit) Memory technology devices (MTD) Char and misc drivers NAND flash

v7 of 9 Superseded Latest is v9 →

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PATCH v7 24/28 armv8/ls2085aqds: NAND boot support

From: Scott Wood <[email protected]>

This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README.

Signed-off-by Scott Wood <[email protected]>
Signed-off-by York Sun <[email protected]>

---

Changes in v7:
Move NAND boot instruction to fsl-lsch3/README.
Update board setting to put RCW and u-boot in different NAND block.

Changes in v6: None
Changes in v5:
Update LS2085AQDS README to include instructions to form NAND image

Changes in v4:
Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                                  |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/README               |   37 +++++++++++
 arch/arm/cpu/armv8/fsl-lsch3/soc.c                |   48 +++++++++++++
 arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} |   74 +++++++++------------
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    9 +++
 arch/arm/lib/crt0_64.S                            |    7 ++
 board/freescale/ls2085aqds/MAINTAINERS            |    1 +
 board/freescale/ls2085aqds/ddr.c                  |    4 ++
 common/spl/spl.c                                  |    2 +-
 common/spl/spl_nand.c                             |    2 +-
 configs/ls2085aqds_nand_defconfig                 |    4 ++
 drivers/misc/fsl_ifc.c                            |   12 ++++
 drivers/mtd/nand/fsl_ifc_spl.c                    |    2 +-
 include/configs/ls2085a_common.h                  |   29 ++++++++
 include/configs/ls2085aqds.h                      |   50 ++++++++++++--
 15 files changed, 231 insertions(+), 51 deletions(-)
 copy arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} (57%)
 create mode 100644 configs/ls2085aqds_nand_defconfig
arch/arm/Kconfig +1 -0
index 6ba4b8d..f73541c 100644
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
 	bool "Support ls2085aqds"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085AQDS platform
 	  The LS2085A Development System (QDS) is a high-performance
arch/arm/cpu/armv8/fsl-lsch3/README +37 -0
index 4f36e2a..eee0228 100644
@@ -95,3 +95,40 @@ mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
 
 mcmemsize:	MC DRAM block size. If this variable is not defined, the value
 		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC		should match the cfg_rcw_src, the reset config pins.
+SRC_ADDR	is the offset of u-boot image in NAND device. It should match
+		CONFIG_SYS_NAND_U_BOOT_OFFS. In the example above, it is 512KB.
+DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE	is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+
+The u-boot image should be written to the offset CONFIG_SYS_NAND_U_BOOT_OFFS,
+in above example 0x80000.
+
+nand write <u-boot image in memory> 80000 <size of u-boot image>
+
+With these two images in NAND device, the board can boot from NAND.
arch/arm/cpu/armv8/fsl-lsch3/soc.c +48 -0

64 lines not on this page · raw message

arch/arm/cpu/armv8/u-boot-spl.lds renamed from arch/arm/cpu/armv8/u-boot.lds +31 -43

111 lines not on this page · raw message

arch/arm/include/asm/arch-fsl-lsch3/config.h +9 -0
index 403b2ef..77c20ab 100644
@@ -130,6 +130,15 @@
 #define CCI_MN_DVM_DOMAIN_CTL		0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
 
+/* Device Configuration */
+#define DCFG_BASE		0x01e00000
+#define DCFG_PORSR1			0x000
+#define DCFG_PORSR1_RCW_SRC		0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+
+#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_PORCR1		0x000
+
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
arch/arm/lib/crt0_64.S +7 -0
index 7756396..bf4ca99 100644
@@ -61,13 +61,18 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	x0, =(CONFIG_SPL_STACK)
+#else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
 	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
 	mov	x18, sp			/* GD is above SP */
 	mov	x0, #0
 	bl	board_init_f
 
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * Set up intermediate environment (new sp and gd) and call
  * relocate_code(addr_moni). Trick here is that we'll return

@@ -110,4 +115,6 @@ clear_loop:
 
 	/* NOTREACHED - board_init_r() does not return */
 
+#endif /* !CONFIG_SPL_BUILD */
+
 ENDPROC(_main)
board/freescale/ls2085aqds/MAINTAINERS +1 -0
index 74b3721..fbed672 100644
@@ -5,3 +5,4 @@ F:	board/freescale/ls2085aqds/
 F:	board/freescale/ls2085a/ls2085aqds.c
 F:	include/configs/ls2085aqds.h
 F:	configs/ls2085aqds_defconfig
+F:	configs/ls2085aqds_nand_defconfig
board/freescale/ls2085aqds/ddr.c +4 -0
index 6cd5e8b..8d71ae1 100644
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	return fsl_ddr_sdram_size();
+#else
 	puts("Initializing DDR....using SPD\n");
 
 	dram_size = fsl_ddr_sdram();
+#endif
 
 	return dram_size;
 }
common/spl/spl.c +1 -1
index cd75bbc..6d5cb0e 100644
@@ -113,7 +113,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	typedef void __noreturn (*image_entry_noargs_t)(void);
 
 	image_entry_noargs_t image_entry =
-			(image_entry_noargs_t) spl_image->entry_point;
+		(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
 
 	debug("image entry point: 0x%X\n", spl_image->entry_point);
 	image_entry();
common/spl/spl_nand.c +1 -1
index b7801cb..b8c369d 100644
@@ -91,7 +91,7 @@ void spl_nand_load_image(void)
 		sizeof(*header), (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-		spl_image.size, (void *)spl_image.load_addr);
+		spl_image.size, (void *)(unsigned long)spl_image.load_addr);
 	nand_deselect();
 }
 #endif
configs/ls2085aqds_nand_defconfig new file +4 -0
new file mode 100644
index 0000000..446206a
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085AQDS=y
drivers/misc/fsl_ifc.c +12 -0
index 45d299c..a33efdb 100644
@@ -168,13 +168,25 @@ void init_final_memctl_regs(void)
 #ifdef CONFIG_SYS_CSPR0_FINAL
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
 #endif
+#ifdef CONFIG_SYS_AMASK0_FINAL
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#endif
 #ifdef CONFIG_SYS_CSPR1_FINAL
 	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
 #endif
 #ifdef CONFIG_SYS_AMASK1_FINAL
 	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
 #endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#endif
 #ifdef CONFIG_SYS_CSPR3_FINAL
 	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
 #endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#endif
 }
drivers/mtd/nand/fsl_ifc_spl.c +1 -1
index 2fb9fb1..fccbfb5 100644
@@ -66,7 +66,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 {
 	struct fsl_ifc_runtime *ifc = runtime_regs_address();
 	u32 status;
-	u32 eccstat[4];
+	u32 eccstat[8];
 	int bufperpage = page_size / 512;
 	int bufnum_end, i;
include/configs/ls2085a_common.h +29 -0
index 44c6845..9bc3869 100644
@@ -28,7 +28,11 @@
 #define CONFIG_ARCH_MISC_INIT
 
 /* Link Definitions */
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_TEXT_BASE		0x80400000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x30100000
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH

@@ -47,7 +51,9 @@
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 
+#ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#endif
 #ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
 #define CONFIG_SYS_DDR_RAW_TIMING

@@ -272,4 +278,27 @@ unsigned long get_dram_size_to_hide(void);
 
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MAX_SIZE		0x16000
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE		0x1800a000
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
 #endif /* __LS2_COMMON_H */
include/configs/ls2085aqds.h +45 -5

78 lines not on this page · raw message

Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v7 26/28 armv8/ls2085ardb: Enable NAND SPL support

From: Scott Wood <[email protected]>

Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README.

Signed-off-by Scott Wood <[email protected]>
Signed-off-by York Sun <[email protected]>

---

Changes in v7:
Move NAND boot instruction to fsl-lsch3/README.
Update board setting to put RCW and u-boot in different NAND block.

Changes in v6: None
Changes in v5:
Fix signed-off-by signature
Update LS2085ARDB README to include instructions to form NAND image

Changes in v4:
Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                       |    1 +
 board/freescale/ls2085ardb/MAINTAINERS |    1 +
 board/freescale/ls2085ardb/ddr.c       |    4 ++++
 configs/ls2085ardb_nand_defconfig      |    4 ++++
 include/configs/ls2085ardb.h           |   40 ++++++++++++++++++++++++++++----
 5 files changed, 45 insertions(+), 5 deletions(-)
 create mode 100644 configs/ls2085ardb_nand_defconfig
arch/arm/Kconfig +1 -0
index f73541c..cf291c8 100644
@@ -663,6 +663,7 @@ config TARGET_LS2085ARDB
 	bool "Support ls2085ardb"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085ARDB platform.
 	  The LS2085A Reference design board (RDB) is a high-performance
board/freescale/ls2085ardb/MAINTAINERS +1 -0
index 436039f..d5cce40 100644
@@ -5,3 +5,4 @@ F:	board/freescale/ls2085ardb/
 F:	board/freescale/ls2085a/ls2085ardb.c
 F:	include/configs/ls2085ardb.h
 F:	configs/ls2085ardb_defconfig
+F:	configs/ls2085ardb_nand_defconfig
board/freescale/ls2085ardb/ddr.c +4 -0
index 6cd5e8b..8d71ae1 100644
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	return fsl_ddr_sdram_size();
+#else
 	puts("Initializing DDR....using SPD\n");
 
 	dram_size = fsl_ddr_sdram();
+#endif
 
 	return dram_size;
 }
configs/ls2085ardb_nand_defconfig new file +4 -0
new file mode 100644
index 0000000..39ba8c5
@@ -0,0 +1,4 @@
++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
++S:CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085ARDB=y
include/configs/ls2085ardb.h +35 -5
index 0a5873b..ae5c2a9 100644
@@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RST_CTL_RESET_EN		0x30
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x119
 #define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0x0)

@@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
 					FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(2048 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR

@@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

@@ -232,11 +267,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
-#define CONFIG_ENV_SECT_SIZE		0x20000
-#define CONFIG_ENV_SIZE			0x2000
-
 #define CONFIG_FSL_MEMAC
 #define CONFIG_PCI		/* Enable PCIE */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v7 24/28 armv8/ls2085aqds: NAND boot support

In reply to York Sun
Quoted 71 lines · York Sun

From: Scott Wood <[email protected]>

This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README.

Signed-off-by Scott Wood <[email protected]>
Signed-off-by York Sun <[email protected]>

---

Changes in v7:
Move NAND boot instruction to fsl-lsch3/README.
Update board setting to put RCW and u-boot in different NAND block.

Changes in v6: None
Changes in v5:
Update LS2085AQDS README to include instructions to form NAND image

Changes in v4:
Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                                  |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/README               |   37 +++++++++++
 arch/arm/cpu/armv8/fsl-lsch3/soc.c                |   48 +++++++++++++
 arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} |   74 +++++++++------------
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    9 +++
 arch/arm/lib/crt0_64.S                            |    7 ++
 board/freescale/ls2085aqds/MAINTAINERS            |    1 +
 board/freescale/ls2085aqds/ddr.c                  |    4 ++
 common/spl/spl.c                                  |    2 +-
 common/spl/spl_nand.c                             |    2 +-
 configs/ls2085aqds_nand_defconfig                 |    4 ++
 drivers/misc/fsl_ifc.c                            |   12 ++++
 drivers/mtd/nand/fsl_ifc_spl.c                    |    2 +-
 include/configs/ls2085a_common.h                  |   29 ++++++++
 include/configs/ls2085aqds.h                      |   50 ++++++++++++--
 15 files changed, 231 insertions(+), 51 deletions(-)
 copy arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} (57%)
 create mode 100644 configs/ls2085aqds_nand_defconfig
arch/arm/Kconfig +1 -0
index 6ba4b8d..f73541c 100644
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
 	bool "Support ls2085aqds"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085AQDS platform
 	  The LS2085A Development System (QDS) is a high-performance
arch/arm/cpu/armv8/fsl-lsch3/README +8 -0
index 4f36e2a..eee0228 100644
@@ -95,3 +95,40 @@ mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
 
 mcmemsize:	MC DRAM block size. If this variable is not defined, the value
 		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000

arch/arm/cpu/armv8/fsl-lsch3/README mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined · line 115

Quoted 10 lines
arch/arm/cpu/armv8/fsl-lsch3/README +10 -0
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC		should match the cfg_rcw_src, the reset config pins.

You should make it clear that this value depends on the type of NAND chip, and that the value for the QDS board is 0x107...

arch/arm/cpu/armv8/fsl-lsch3/README mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined · line 127

Quoted 12 lines
arch/arm/cpu/armv8/fsl-lsch3/README +12 -0
+SRC_ADDR	is the offset of u-boot image in NAND device. It should match
+		CONFIG_SYS_NAND_U_BOOT_OFFS. In the example above, it is 512KB.
+DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE	is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.

...especially since this makes it look like the above example is for QDS.

-Scott

author
#3 lore raw

PATCH v7 24/28 armv8/ls2085aqds: NAND boot support

Quoted 77 lines · Scott Wood
Quoted 76 lines · York Sun

From: Scott Wood <[email protected]>

This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README.

Signed-off-by Scott Wood <[email protected]>
Signed-off-by York Sun <[email protected]>

---

Changes in v7:
Move NAND boot instruction to fsl-lsch3/README.
Update board setting to put RCW and u-boot in different NAND block.

Changes in v6: None
Changes in v5:
Update LS2085AQDS README to include instructions to form NAND image

Changes in v4:
Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig                                  |    1 +
 arch/arm/cpu/armv8/fsl-lsch3/README               |   37 +++++++++++
 arch/arm/cpu/armv8/fsl-lsch3/soc.c                |   48 +++++++++++++
 arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} |   74 +++++++++------------
 arch/arm/include/asm/arch-fsl-lsch3/config.h      |    9 +++
 arch/arm/lib/crt0_64.S                            |    7 ++
 board/freescale/ls2085aqds/MAINTAINERS            |    1 +
 board/freescale/ls2085aqds/ddr.c                  |    4 ++
 common/spl/spl.c                                  |    2 +-
 common/spl/spl_nand.c                             |    2 +-
 configs/ls2085aqds_nand_defconfig                 |    4 ++
 drivers/misc/fsl_ifc.c                            |   12 ++++
 drivers/mtd/nand/fsl_ifc_spl.c                    |    2 +-
 include/configs/ls2085a_common.h                  |   29 ++++++++
 include/configs/ls2085aqds.h                      |   50 ++++++++++++--
 15 files changed, 231 insertions(+), 51 deletions(-)
 copy arch/arm/cpu/armv8/{u-boot.lds => u-boot-spl.lds} (57%)
 create mode 100644 configs/ls2085aqds_nand_defconfig
arch/arm/Kconfig +1 -0
index 6ba4b8d..f73541c 100644
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
 	bool "Support ls2085aqds"
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2085AQDS platform
 	  The LS2085A Development System (QDS) is a high-performance
arch/arm/cpu/armv8/fsl-lsch3/README +13 -0
index 4f36e2a..eee0228 100644
@@ -95,3 +95,40 @@ mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
 
 mcmemsize:	MC DRAM block size. If this variable is not defined, the value
 		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
Quoted 8 lines

arch/arm/cpu/armv8/fsl-lsch3/README mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined · line 115

Quoted 5 lines
arch/arm/cpu/armv8/fsl-lsch3/README +5 -0
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC		should match the cfg_rcw_src, the reset config pins.

You should make it clear that this value depends on the type of NAND chip, and that the value for the QDS board is 0x107...

OK. I will 0x107 here and add 0x119 with RDB patch.

Quoted 16 lines

arch/arm/cpu/armv8/fsl-lsch3/README mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined · line 127

Quoted 13 lines
arch/arm/cpu/armv8/fsl-lsch3/README +12 -0
+SRC_ADDR	is the offset of u-boot image in NAND device. It should match
+		CONFIG_SYS_NAND_U_BOOT_OFFS. In the example above, it is 512KB.
+DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE	is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.

...especially since this makes it look like the above example is for QDS.

Make sense.

York