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clk: qcom: gdsc: Add GDSCs in apq8084 MMCC

PATCH In review Stephane Viau 2 participants 3 messages Mar 25, 2015 – Mar 26, 2015

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Stephane Viau

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#0 lore raw

PATCH 1/1 clk: qcom: gdsc: Add GDSCs in apq8084 MMCC

Add the GDSC instances that exist as part of apq8084 MMCC block.

Signed-off-by Stephane Viau <[email protected]>
---
 drivers/clk/qcom/Kconfig                      |  1 +
 drivers/clk/qcom/mmcc-apq8084.c               | 56 ++++++++++++++++++++++++++-
 include/dt-bindings/clock/qcom,mmcc-apq8084.h |  8 ++++
 3 files changed, 64 insertions(+), 1 deletion(-)
drivers/clk/qcom/Kconfig +1 -0
index 4dadfc9..89879e1 100644
@@ -15,6 +15,7 @@ config APQ_GCC_8084
 config APQ_MMCC_8084
 	tristate "APQ8084 Multimedia Clock Controller"
 	select APQ_GCC_8084
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on apq8084 devices.
drivers/clk/qcom/mmcc-apq8084.c +55 -1

84 lines not on this page · raw message

include/dt-bindings/clock/qcom,mmcc-apq8084.h +8 -0
index d72b5b3..21fec5d 100644
@@ -180,4 +180,12 @@
 #define VPU_SLEEP_CLK			163
 #define VPU_VDP_CLK			164
 
+/* GDSCs */
+#define VENUS0_GDSC			0
+#define MDSS_GDSC			1
+#define CAMSS_JPEG_GDSC			2
+#define CAMSS_VFE_GDSC			3
+#define OXILI_GDSC			4
+#define OXILICX_GDSC			5
+
 #endif
Signature · 3 lines
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
#1 lore raw
Quoted 90 lines · Stephane Viau

Add the GDSC instances that exist as part of apq8084 MMCC block.

Signed-off-by Stephane Viau <[email protected]>
---
  drivers/clk/qcom/Kconfig                      |  1 +
  drivers/clk/qcom/mmcc-apq8084.c               | 56 ++++++++++++++++++++++++++-
  include/dt-bindings/clock/qcom,mmcc-apq8084.h |  8 ++++
  3 files changed, 64 insertions(+), 1 deletion(-)
drivers/clk/qcom/Kconfig +1 -0
index 4dadfc9..89879e1 100644
@@ -15,6 +15,7 @@ config APQ_GCC_8084
  config APQ_MMCC_8084
  	tristate "APQ8084 Multimedia Clock Controller"
  	select APQ_GCC_8084
+	select QCOM_GDSC
  	depends on COMMON_CLK_QCOM
  	help
  	  Support for the multimedia clock controller on apq8084 devices.
drivers/clk/qcom/mmcc-apq8084.c +44 -1
index 157139a..626adbd 100644
@@ -1,5 +1,5 @@
  /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   *
   * This software is licensed under the terms of the GNU General Public
   * License version 2, as published by the Free Software Foundation, and

@@ -26,6 +26,7 @@
  #include "clk-rcg.h"
  #include "clk-branch.h"
  #include "reset.h"
+#include "gdsc.h"
 
  #define P_XO		0
  #define P_MMPLL0	1

@@ -3075,6 +3076,48 @@ static const struct pll_config mmpll3_config = {
  	.aux_output_mask = BIT(1),
  };
 
+static struct gdsc venus0_gdsc = {
+	.gdscr = 0x1024,
+	.pd = {
+		.name = "venus0",
+	},
+};
+
+static struct gdsc mdss_gdsc = {
+	.gdscr = 0x2304,
+	.pd = {
+		.name = "mdss",
+	},
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+	.gdscr = 0x35a4,
+	.pd = {
+		.name = "camss_jpeg",
+	},
+};
+
+static struct gdsc camss_vfe_gdsc = {
+	.gdscr = 0x36a4,
+	.pd = {
+		.name = "camss_vfe",
+	},
+};
+
+static struct gdsc oxili_gdsc = {
+	.gdscr = 0x4024,
+	.pd = {
+		.name = "oxili",
+	},
+};
+
+static struct gdsc oxilicx_gdsc = {
+	.gdscr = 0x4034,
+	.pd = {
+		.name = "oxilicx",
+	},
+};
+
  static struct clk_regmap *mmcc_apq8084_clocks[] = {
  	[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
  	[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,

drivers/clk/qcom/mmcc-apq8084.c static const struct qcom_reset_map mmcc_apq8084_resets[] = { · line 3338

Quoted 4 lines
drivers/clk/qcom/mmcc-apq8084.c +1 -0
@@ -3292,6 +3335,15 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = {
  	[MMSSNOCAXI_RESET] = { 0x5060 },
  };
 
+static struct generic_pm_domain *mmcc_apq8084_gdscs[] = {

With my v3, I changed this to an array of struct gdsc, I will update this patch and include it in my gdsc series v4 repost, that I will do shortly.

regards,
Rajendra

Quoted 38 lines
drivers/clk/qcom/mmcc-apq8084.c +10 -0
+	[VENUS0_GDSC] = &venus0_gdsc.pd,
+	[MDSS_GDSC] = &mdss_gdsc.pd,
+	[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc.pd,
+	[CAMSS_VFE_GDSC] = &camss_vfe_gdsc.pd,
+	[OXILI_GDSC] = &oxili_gdsc.pd,
+	[OXILICX_GDSC] = &oxilicx_gdsc.pd,
+};
+
  static const struct regmap_config mmcc_apq8084_regmap_config = {
  	.reg_bits	= 32,
  	.reg_stride	= 4,

@@ -3306,6 +3358,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
  	.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
  	.resets = mmcc_apq8084_resets,
  	.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+	.gdscs = mmcc_apq8084_gdscs,
+	.num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
  };
 
  static const struct of_device_id mmcc_apq8084_match_table[] = {
include/dt-bindings/clock/qcom,mmcc-apq8084.h +8 -0
index d72b5b3..21fec5d 100644
@@ -180,4 +180,12 @@
  #define VPU_SLEEP_CLK			163
  #define VPU_VDP_CLK			164
 
+/* GDSCs */
+#define VENUS0_GDSC			0
+#define MDSS_GDSC			1
+#define CAMSS_JPEG_GDSC			2
+#define CAMSS_VFE_GDSC			3
+#define OXILI_GDSC			4
+#define OXILICX_GDSC			5
+
  #endif
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
author
#2 lore raw
Quoted 97 lines · Stephane Viau
Quoted 6 lines

Add the GDSC instances that exist as part of apq8084 MMCC block.

Signed-off-by Stephane Viau <[email protected]>
---
  drivers/clk/qcom/Kconfig                      |  1 +
  drivers/clk/qcom/mmcc-apq8084.c               | 56

++++++++++++++++++++++++++-

Review

Quoted 16 lines
  include/dt-bindings/clock/qcom,mmcc-apq8084.h |  8 ++++
  3 files changed, 64 insertions(+), 1 deletion(-)
drivers/clk/qcom/Kconfig +1 -0
index 4dadfc9..89879e1 100644
@@ -15,6 +15,7 @@ config APQ_GCC_8084
  config APQ_MMCC_8084
  	tristate "APQ8084 Multimedia Clock Controller"
  	select APQ_GCC_8084
+	select QCOM_GDSC
  	depends on COMMON_CLK_QCOM
  	help
  	  Support for the multimedia clock controller on apq8084 devices.
(quoted diff) +0 -0

b/drivers/clk/qcom/mmcc-apq8084.c

drivers/clk/qcom/mmcc-apq8084.c line 5

Quoted 10 lines

index 157139a..626adbd 100644

drivers/clk/qcom/mmcc-apq8084.c +1 -1
@@ -1,5 +1,5 @@
  /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   *
   * This software is licensed under the terms of the GNU General Public
   * License version 2, as published by the Free Software Foundation,

and

drivers/clk/qcom/mmcc-apq8084.c static const struct qcom_reset_map

Quoted 58 lines
drivers/clk/qcom/mmcc-apq8084.c +43 -0
@@ -26,6 +26,7 @@
  #include "clk-rcg.h"
  #include "clk-branch.h"
  #include "reset.h"
+#include "gdsc.h"
 
  #define P_XO		0
  #define P_MMPLL0	1

@@ -3075,6 +3076,48 @@ static const struct pll_config mmpll3_config = {
  	.aux_output_mask = BIT(1),
  };
 
+static struct gdsc venus0_gdsc = {
+	.gdscr = 0x1024,
+	.pd = {
+		.name = "venus0",
+	},
+};
+
+static struct gdsc mdss_gdsc = {
+	.gdscr = 0x2304,
+	.pd = {
+		.name = "mdss",
+	},
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+	.gdscr = 0x35a4,
+	.pd = {
+		.name = "camss_jpeg",
+	},
+};
+
+static struct gdsc camss_vfe_gdsc = {
+	.gdscr = 0x36a4,
+	.pd = {
+		.name = "camss_vfe",
+	},
+};
+
+static struct gdsc oxili_gdsc = {
+	.gdscr = 0x4024,
+	.pd = {
+		.name = "oxili",
+	},
+};
+
+static struct gdsc oxilicx_gdsc = {
+	.gdscr = 0x4034,
+	.pd = {
+		.name = "oxilicx",
+	},
+};
+
  static struct clk_regmap *mmcc_apq8084_clocks[] = {
  	[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
  	[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,

@@ -3292,6 +3335,15 @@ static const struct qcom_reset_map

mmcc_apq8084_resets[] = {

Quoted 8 lines

drivers/clk/qcom/mmcc-apq8084.c static const struct qcom_reset_map mmcc_apq8084_resets[] = { · line 3338

Quoted 4 lines
drivers/clk/qcom/mmcc-apq8084.c +1 -0
  	[MMSSNOCAXI_RESET] = { 0x5060 },
  };
 
+static struct generic_pm_domain *mmcc_apq8084_gdscs[] = {

With my v3, I changed this to an array of struct gdsc, I will update this patch and include it in my gdsc series v4 repost, that I will do shortly.

Thanks for rebasing, Rajendra.

Regards,
Stephane.

Quoted 49 lines

regards,
Rajendra

drivers/clk/qcom/mmcc-apq8084.c static const struct qcom_cc_desc mmcc_apq8084_desc

Quoted 12 lines
drivers/clk/qcom/mmcc-apq8084.c +8 -0
+	[VENUS0_GDSC] = &venus0_gdsc.pd,
+	[MDSS_GDSC] = &mdss_gdsc.pd,
+	[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc.pd,
+	[CAMSS_VFE_GDSC] = &camss_vfe_gdsc.pd,
+	[OXILI_GDSC] = &oxili_gdsc.pd,
+	[OXILICX_GDSC] = &oxilicx_gdsc.pd,
+};
+
  static const struct regmap_config mmcc_apq8084_regmap_config = {
  	.reg_bits	= 32,
  	.reg_stride	= 4,

@@ -3306,6 +3358,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc

= {

Review

Quoted 9 lines
drivers/clk/qcom/mmcc-apq8084.c +2 -0
  	.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
  	.resets = mmcc_apq8084_resets,
  	.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+	.gdscs = mmcc_apq8084_gdscs,
+	.num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
  };
 
  static const struct of_device_id mmcc_apq8084_match_table[] = {
(quoted diff) +0 -0

b/include/dt-bindings/clock/qcom,mmcc-apq8084.h

Quoted 7 lines

index d72b5b3..21fec5d 100644

include/dt-bindings/clock/qcom,mmcc-apq8084.h +0 -0
@@ -180,4 +180,12 @@
  #define VPU_SLEEP_CLK			163
  #define VPU_VDP_CLK			164

include/dt-bindings/clock/qcom,mmcc-apq8084.h line 191

Quoted 10 lines
include/dt-bindings/clock/qcom,mmcc-apq8084.h +8 -0
 
+/* GDSCs */
+#define VENUS0_GDSC			0
+#define MDSS_GDSC			1
+#define CAMSS_JPEG_GDSC			2
+#define CAMSS_VFE_GDSC			3
+#define OXILI_GDSC			4
+#define OXILICX_GDSC			5
+
  #endif

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Signature · 4 lines
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project