ARM: dts: Add HS400 support for exynos5422-odroidxu3

PATCH Superseded Markus Reichl 2 participants 4 messages Mar 30, 2015 – Apr 8, 2015

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Markus Reichl

author

2015-03-30 15:51 UTC #0 lore raw

PATCH 1/1 ARM: dts: Add HS400 support for exynos5422-odroidxu3

HS400 timing values are added for exynos5422-odroidxu3 board.
---
This patch is analog to [0].
This patch needs [0] for the pin-ctrl definition of sd0_rclk.

[0]: https://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg42902.html

Signed-off-by Markus Reichl <[email protected]>

---
 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

arch/arm/boot/dts/exynos5422-odroidxu3.dts +6 -1

index a519c86..0408ec0 100644
@@ -298,15 +298,20 @@
 
 &mmc_0 {
 	status = "okay";
+	num-slots = <1>;
 	broken-cd;
 	card-detect-delay = <200>;
 	samsung,dw-mshc-ciu-div = <3>;
 	samsung,dw-mshc-sdr-timing = <0 4>;
 	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 };
 
 &mmc_2 {

Signature · 1 line

1.9.1

Markus Reichl

author

2015-03-31 12:27 UTC #1 lore raw

Am 30.03.2015 um 17:51 schrieb Markus Reichl:

Quoted 29 lines

HS400 timing values are added for exynos5422-odroidxu3 board.
---
This patch is analog to [0].
This patch needs [0] for the pin-ctrl definition of sd0_rclk.
[0]: https://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg42902.html
Signed-off-by Markus Reichl <[email protected]>
---
 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -0
index a519c86..0408ec0 100644
@@ -298,15 +298,20 @@
 
 &mmc_0 {
 	status = "okay";
+	num-slots = <1>;
 	broken-cd;
 	card-detect-delay = <200>;
 	samsung,dw-mshc-ciu-div = <3>;
 	samsung,dw-mshc-sdr-timing = <0 4>;
 	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;

arch/arm/boot/dts/exynos5422-odroidxu3.dts line 317

Quoted 10 lines

arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -1

 	pinctrl-names = "default";
-	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 };
 
 &mmc_2 {

hdparm -t /dev/mmcblk0

without this patch:
/dev/mmcblk0:
Timing buffered disk reads: 230 MB in 3.01 seconds = 76.30 MB/sec

with this patch:
/dev/mmcblk0:
Timing buffered disk reads: 588 MB in 3.00 seconds = 195.92 MB/sec

cat /sys/kernel/debug/mmc0/ios

without patch:

clock:          52000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 0 (1.80 V)

with patch:

clock:          200000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    10 (mmc HS400)
signal voltage: 0 (1.80 V)

Best Regards

Signature · 1 line

Markus Reichl

Markus Reichl

author Tested-by Anand Moon

2015-04-07 15:33 UTC #2 lore raw

Hi,

the base patch in [0] has been applied now.

My patch was meanwhile

Tested-by Anand Moon <[email protected]>

Am 31.03.2015 um 14:27 schrieb Markus Reichl:

Quoted 75 lines

Am 30.03.2015 um 17:51 schrieb Markus Reichl:
Quoted 29 lines
HS400 timing values are added for exynos5422-odroidxu3 board.
---
This patch is analog to [0].
This patch needs [0] for the pin-ctrl definition of sd0_rclk.
[0]: https://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg42902.html
Signed-off-by Markus Reichl <[email protected]>
---
 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -0
index a519c86..0408ec0 100644
@@ -298,15 +298,20 @@
 
 &mmc_0 {
 	status = "okay";
+	num-slots = <1>;
 	broken-cd;
 	card-detect-delay = <200>;
 	samsung,dw-mshc-ciu-div = <3>;
 	samsung,dw-mshc-sdr-timing = <0 4>;
 	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;
arch/arm/boot/dts/exynos5422-odroidxu3.dts line 317
Quoted 10 lines
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -1
 	pinctrl-names = "default";
-	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 };
 
 &mmc_2 {
hdparm -t /dev/mmcblk0
without this patch:
/dev/mmcblk0:
Timing buffered disk reads: 230 MB in 3.01 seconds = 76.30 MB/sec
with this patch:
/dev/mmcblk0:
Timing buffered disk reads: 588 MB in 3.00 seconds = 195.92 MB/sec
cat /sys/kernel/debug/mmc0/ios
without patch:
clock:          52000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 0 (1.80 V)
with patch:
clock:          200000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    10 (mmc HS400)
signal voltage: 0 (1.80 V)
Best Regards

Signature · 1 line

Markus Reichl

Jaehoon Chung

Acked-by

2015-04-08 00:37 UTC #3 lore raw

Hi, Markus.

I have also tested on Odroid-xu3 board.

Acked-by Jaehoon Chung <[email protected]>

Best Regards,
Jaehoon Chung

Quoted 87 lines · Markus Reichl

Hi,
the base patch in [0] has been applied now.
My patch was meanwhile
Tested-by Anand Moon <[email protected]>
Am 31.03.2015 um 14:27 schrieb Markus Reichl:
Quoted 75 lines
Am 30.03.2015 um 17:51 schrieb Markus Reichl:
Quoted 29 lines
HS400 timing values are added for exynos5422-odroidxu3 board.
---
This patch is analog to [0].
This patch needs [0] for the pin-ctrl definition of sd0_rclk.
[0]: https://www.mail-archive.com/linux-samsung-soc%40vger.kernel.org/msg42902.html
Signed-off-by Markus Reichl <[email protected]>
---
 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -0
index a519c86..0408ec0 100644
@@ -298,15 +298,20 @@
 
 &mmc_0 {
 	status = "okay";
+	num-slots = <1>;
 	broken-cd;
 	card-detect-delay = <200>;
 	samsung,dw-mshc-ciu-div = <3>;
 	samsung,dw-mshc-sdr-timing = <0 4>;
 	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;
arch/arm/boot/dts/exynos5422-odroidxu3.dts line 317
Quoted 10 lines
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -1
 	pinctrl-names = "default";
-	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 };
 
 &mmc_2 {
hdparm -t /dev/mmcblk0
without this patch:
/dev/mmcblk0:
Timing buffered disk reads: 230 MB in 3.01 seconds = 76.30 MB/sec
with this patch:
/dev/mmcblk0:
Timing buffered disk reads: 588 MB in 3.00 seconds = 195.92 MB/sec
cat /sys/kernel/debug/mmc0/ios
without patch:
clock:          52000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 0 (1.80 V)
with patch:
clock:          200000000 Hz
vdd:            7 (1.65 - 1.95 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    10 (mmc HS400)
signal voltage: 0 (1.80 V)
Best Regards