peach_pi: Add support for FIMD and DP

index c6455c2..8bee324 100644
@@ -14,7 +14,6 @@
 #define PLL_DIV_1024	1024
 #define PLL_DIV_65535	65535
 #define PLL_DIV_65536	65536
-
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers

@@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * CLKMUX_FIMD1 [6:4]
+	 */
+	sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+	if (sel) {
+		/*
+		 * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+		 * PLLs. The first element is a placeholder to bypass the
+		 * default settig.
+		 */
+		const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+									RPLL};
+		sclk = get_pll_clk(reg_map[sel]);
+	} else
+		sclk = CONFIG_SYS_CLK_FREQ;
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10) & 0xf;
+
+	return sclk / (ratio + 1);
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =

@@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void)
 	writel(cfg, &clk->div_disp10);
 }
 
+void exynos5800_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * Use RPLL for pixel clock
+	 * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+	 * ==================
+	 * 111: SCLK_RPLL
+	 */
+	cfg = readl(&clk->src_disp10) | (0x7 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =

@@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void)
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
 	else {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420())
 			return exynos5420_get_lcd_clk();
+		else if (proid_is_exynos5800())
+			return exynos5800_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();
 	}

@@ -1660,8 +1717,10 @@ void set_lcd_clk(void)
 	else {
 		if (proid_is_exynos5250())
 			exynos5_set_lcd_clk();
-		else if (proid_is_exynos5420() || proid_is_exynos5800())
+		else if (proid_is_exynos5420())
 			exynos5420_set_lcd_clk();
+		else
+			exynos5800_set_lcd_clk();
 	}
 }
 

index 2a17dfc..d20b7d2 100644
@@ -16,6 +16,9 @@
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9
+#define IPLL	10
 
 #define MASK_PRE_RATIO(x)	(0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)		(0xf << (x << 4))

index 0aff3d0..0200fd1 100644
@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
 		.spll_mdiv = 0xc8,
 		.spll_pdiv = 0x3,
 		.spll_sdiv = 0x2,
-		/* RPLL @70.5Mhz */
+		/* RPLL @141Mhz */
 		.rpll_mdiv = 0x5E,
 		.rpll_pdiv = 0x2,
-		.rpll_sdiv = 0x4,
+		.rpll_sdiv = 0x3,
 
 		.direct_cmd_msr = {
 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,

index c5d7330..8f3b826 100644
@@ -19,6 +19,7 @@
 #include <asm/arch/mipi_dsim.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/system.h>
+#include <asm/gpio.h>
 #include <asm-generic/errno.h>
 
 #include "exynos_fb.h"

@@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
 
 static void lcd_panel_on(vidinfo_t *vid)
 {
+	struct gpio_desc pwm_out_gpio;
+	struct gpio_desc bl_en_gpio;
+	unsigned int node;
+
 	udelay(vid->init_delay);
 
 	exynos_backlight_reset();

@@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid)
 
 	exynos_backlight_on(1);
 
+#ifdef CONFIG_OF_CONTROL
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+						COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0) {
+		debug("FIMD: Can't get device node for FIMD\n");
+		return;
+	}
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
+				   0, &pwm_out_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
+				   &bl_en_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+#endif
 	exynos_cfg_ldo();
 
 	exynos_enable_ldo(1);

index 0f543f6..ae50971 100644
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdtdec.h>
+#include <asm/gpio.h>
 
 /*
  * Initialization of the chip is a process of writing certaing values into

@@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table)
 
 int parade_init(const void *blob)
 {
+	struct gpio_desc rst_gpio;
+	struct gpio_desc slp_gpio;
 	int bus, old_bus;
 	int parent;
 	int node;

@@ -201,6 +204,14 @@ int parade_init(const void *blob)
 		return -1;
 	}
 
+	gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	mdelay(10);
+
+	gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
 	bus = i2c_get_bus_num_fdt(parent);
 	old_bus = i2c_get_bus_num();
 

index 1aca9fa..82f607b 100644
@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
 
 	mdelay(5);
 
-	/* TODO(ajaykumar.rs at samsung.com): Use device tree */
-	gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
-	gpio_direction_output(EXYNOS5420_GPIO_X35, 1);	/* EDP_SLP# */
-	mdelay(10);
-	gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
-	gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);	/* EDP_RST# */
-	gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
-	gpio_direction_input(EXYNOS5420_GPIO_X26);	/* EDP_HPD */
-	gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
 	if (has_edp_bridge())
 		if (parade_init(gd->fdt_blob))
 			printf("%s: ps8625_init() failed\n", __func__);

@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
 
 void exynos_backlight_on(unsigned int onoff)
 {
-	/* For PWM */
-	gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
-	gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
-	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
 #ifdef CONFIG_POWER_TPS65090
 	tps65090_fet_enable(1);
 #endif