ARM: mx6: Fix errata workarounds for i.MX6

From: Nitin Garg <[email protected]>

Since MX6 is Cortex-A9 r2p10, enable ARM errata
751472, 794072, 761320 only applied to the
following configuration:

This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL.

---

Changes in v3:
Split the patch as suggested by Fabio.

Changes in v2: None

 include/configs/mx6_common.h |    3 +++
 1 file changed, 3 insertions(+)

index e0528ce..e22336e 100644
@@ -18,9 +18,12 @@
 #define __MX6_COMMON_H
 
 #define CONFIG_ARM_ERRATA_743622
+#if (defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) ||\
+defined(CONFIG_MX6QDL)) && !defined(CONFIG_MX6S)
 #define CONFIG_ARM_ERRATA_751472
 #define CONFIG_ARM_ERRATA_794072
 #define CONFIG_ARM_ERRATA_761320
+#endif
 #define CONFIG_BOARD_POSTCLK_INIT
 
 #ifndef CONFIG_SYS_L2CACHE_OFF

1.7.9.5

From: Nitin Garg <[email protected]>

Under very rare timing circumstances, transition into streaming mode might create a data corruption. Exists on all Cortex-A9 revisions.

---

Changes in v3: None
Changes in v2: None

 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+)

index b7c2a17..8976041 100644
@@ -683,6 +683,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
 		CONFIG_ARM_ERRATA_761320
+		CONFIG_ARM_ERRATA_845369
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

index 5ed0f45..db77adb 100644
@@ -164,6 +164,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 21	@ set bit #21
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_845369
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 22	@ set bit #22
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	r5, lr			@ Store my Caller
 	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)

1.7.9.5

From: Nitin Garg <[email protected]>

The ARM errata 845369 only applies to one processor if the ACP is present OR two or more processors. i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL.

---

Changes in v3:
Split the patch as suggested by Fabio.

Changes in v2:
Apply 751472, 794072, 761320, 845369 to i.MX6DQ, i.MX6DL only.

 include/configs/mx6_common.h |    1 +
 1 file changed, 1 insertion(+)

index e22336e..cc6b03e 100644
@@ -23,6 +23,7 @@ defined(CONFIG_MX6QDL)) && !defined(CONFIG_MX6S)
 #define CONFIG_ARM_ERRATA_751472
 #define CONFIG_ARM_ERRATA_794072
 #define CONFIG_ARM_ERRATA_761320
+#define CONFIG_ARM_ERRATA_845369
 #endif
 #define CONFIG_BOARD_POSTCLK_INIT
 

1.7.9.5

Hi Troy, Nitin,

Indeed. If static options seem to work with most of SOC, this forbids having single binary for MX6. We should use some "quirk" as in kernel to provide SOC specific fixes.

I see that there is already a similar case for cp15, and there is a _weak function for it:

void __weak v7_arch_cp15_set_acr(u32,..

and SOC can have there specialties there. Maybe you can add the fix as weak function in ARM code, and then in arch/arm/cpu/armv7/mx6/soc.c you can do the runtime check.

Best regards,
Stefano Babics

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