Skip to contentSkip to conversation

arch: add corei7-avx

PATCH New Steven Noonan 4 participants 10 messages Mar 18, 2015 – Jul 20, 2015

lore
Share & tools
lore

Steven Noonan

author
#0 lore raw

PATCH 1/3 arch: add corei7-avx

Signed-off-by Steven Noonan <[email protected]>
---
 arch/Config.in.x86 | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/Config.in.x86 +13 -0
index d5788b1..9767bc1 100644
@@ -13,6 +13,8 @@ config BR2_X86_CPU_HAS_SSE4
 	bool
 config BR2_X86_CPU_HAS_SSE42
 	bool
+config BR2_X86_CPU_HAS_AVX
+	bool
 
 choice
 	prompt "Target Architecture Variant"

@@ -89,6 +91,16 @@ config BR2_x86_corei7
 	select BR2_X86_CPU_HAS_SSSE3
 	select BR2_X86_CPU_HAS_SSE4
 	select BR2_X86_CPU_HAS_SSE42
+config BR2_x86_corei7_avx
+	bool "corei7-avx"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
+	select BR2_X86_CPU_HAS_SSE4
+	select BR2_X86_CPU_HAS_SSE42
+	select BR2_X86_CPU_HAS_AVX
 config BR2_x86_atom
 	bool "atom"
 	select BR2_X86_CPU_HAS_MMX

@@ -226,6 +238,7 @@ config BR2_GCC_TARGET_ARCH
 	default "nocona"	if BR2_x86_nocona
 	default "core2"		if BR2_x86_core2
 	default "corei7"	if BR2_x86_corei7
+	default "corei7-avx"	if BR2_x86_corei7_avx
 	default "atom"		if BR2_x86_atom
 	default "k8"		if BR2_x86_opteron
 	default "k8-sse3"	if BR2_x86_opteron_sse3
Signature · 1 line
2.3.3
author
#1 lore raw

PATCH 1/1 package/glibc: enable lock elision on x86_64 hosts

Signed-off-by Steven Noonan <[email protected]>
---
 package/glibc/glibc.mk | 1 +
 1 file changed, 1 insertion(+)
package/glibc/glibc.mk +1 -0
index 0a37bb3..651711a 100644
@@ -90,6 +90,7 @@ define GLIBC_CONFIGURE_CMDS
 		--prefix=/usr \
 		--enable-shared \
 		$(if $(BR2_SOFT_FLOAT),--without-fp,--with-fp) \
+		$(if $(BR2_x86_64),--enable-lock-elision,) \
 		--with-pkgversion="Buildroot" \
 		--without-cvs \
 		--disable-profile \
Signature · 1 line
2.3.3
#2 lore raw

PATCH 1/1 package/glibc: enable lock elision on x86_64 hosts

Dear Steven Noonan,

Quoted 10 lines · Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 package/glibc/glibc.mk | 1 +
 1 file changed, 1 insertion(+)
package/glibc/glibc.mk +0 -0
index 0a37bb3..651711a 100644

package/glibc/glibc.mk define GLIBC_CONFIGURE_CMDS · line 93

Quoted 4 lines
package/glibc/glibc.mk +1 -0
@@ -90,6 +90,7 @@ define GLIBC_CONFIGURE_CMDS
 		--prefix=/usr \
 		--enable-shared \
 		$(if $(BR2_SOFT_FLOAT),--without-fp,--with-fp) \
+		$(if $(BR2_x86_64),--enable-lock-elision,) \

What happens on x86-64 processors that don't have the HW support needed for lock elision ? Does glibc gracefully falls back at runtime to "normal" locks ?

Thanks,

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
#3 lore raw

PATCH 1/1 package/glibc: enable lock elision on x86_64 hosts

Hi Thomas,

Quoted 6 lines · Thomas Petazzoni
Quoted 5 lines · Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 package/glibc/glibc.mk | 1 +
 1 file changed, 1 insertion(+)
Quoted 13 lines

package/glibc/glibc.mk define GLIBC_CONFIGURE_CMDS · line 93

Quoted 9 lines
package/glibc/glibc.mk +1 -0
index 0a37bb3..651711a 100644
@@ -90,6 +90,7 @@ define GLIBC_CONFIGURE_CMDS
 		--prefix=/usr \
 		--enable-shared \
 		$(if $(BR2_SOFT_FLOAT),--without-fp,--with-fp) \
+		$(if $(BR2_x86_64),--enable-lock-elision,) \

What happens on x86-64 processors that don't have the HW support needed for lock elision ? Does glibc gracefully falls back at runtime to "normal" locks ?

According to the code at sysdeps/unix/sysv/linux/x86/elision-conf.c, __elision_available is initialized from HAS_RTM which is evaluated at run-time (sysdeps/x86_64/multiarch/init-arch.h).

baruch

Signature · 3 lines
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
#4 lore raw

PATCH 1/1 package/glibc: enable lock elision on x86_64 hosts

In reply to Steven Noonan

Dear Steven Noonan,

Quoted 10 lines · Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 package/glibc/glibc.mk | 1 +
 1 file changed, 1 insertion(+)
package/glibc/glibc.mk +0 -0
index 0a37bb3..651711a 100644

package/glibc/glibc.mk define GLIBC_CONFIGURE_CMDS · line 93

Quoted 4 lines
package/glibc/glibc.mk +1 -0
@@ -90,6 +90,7 @@ define GLIBC_CONFIGURE_CMDS
 		--prefix=/usr \
 		--enable-shared \
 		$(if $(BR2_SOFT_FLOAT),--without-fp,--with-fp) \
+		$(if $(BR2_x86_64),--enable-lock-elision,) \

The last comma was unnecessary. I've removed it and committed, thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
author
#5 lore raw

PATCH 2/3 arch: add core-avx2

In reply to Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 arch/Config.in.x86 | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/Config.in.x86 +14 -0
index 9767bc1..43f6abc 100644
@@ -15,6 +15,8 @@ config BR2_X86_CPU_HAS_SSE42
 	bool
 config BR2_X86_CPU_HAS_AVX
 	bool
+config BR2_X86_CPU_HAS_AVX2
+	bool
 
 choice
 	prompt "Target Architecture Variant"

@@ -101,6 +103,17 @@ config BR2_x86_corei7_avx
 	select BR2_X86_CPU_HAS_SSE4
 	select BR2_X86_CPU_HAS_SSE42
 	select BR2_X86_CPU_HAS_AVX
+config BR2_x86_core_avx2
+	bool "core-avx2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
+	select BR2_X86_CPU_HAS_SSE4
+	select BR2_X86_CPU_HAS_SSE42
+	select BR2_X86_CPU_HAS_AVX
+	select BR2_X86_CPU_HAS_AVX2
 config BR2_x86_atom
 	bool "atom"
 	select BR2_X86_CPU_HAS_MMX

@@ -239,6 +252,7 @@ config BR2_GCC_TARGET_ARCH
 	default "core2"		if BR2_x86_core2
 	default "corei7"	if BR2_x86_corei7
 	default "corei7-avx"	if BR2_x86_corei7_avx
+	default "core-avx2"	if BR2_x86_core_avx2
 	default "atom"		if BR2_x86_atom
 	default "k8"		if BR2_x86_opteron
 	default "k8-sse3"	if BR2_x86_opteron_sse3
Signature · 1 line
2.3.3
author
#7 lore raw

PATCH 3/3 packages: add AVX/AVX2 support to ffmpeg/opencv

In reply to Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 package/ffmpeg/ffmpeg.mk | 12 ++++++++++++
 package/opencv/opencv.mk |  2 ++
 2 files changed, 14 insertions(+)
package/ffmpeg/ffmpeg.mk +12 -0
index 68a28a2..47372df 100644
@@ -301,6 +301,18 @@ else
 FFMPEG_CONF_OPTS += --disable-sse42
 endif
 
+ifeq ($(BR2_X86_CPU_HAS_AVX),y)
+FFMPEG_CONF_OPTS += --enable-avx
+else
+FFMPEG_CONF_OPTS += --disable-avx
+endif
+
+ifeq ($(BR2_X86_CPU_HAS_AVX2),y)
+FFMPEG_CONF_OPTS += --enable-avx2
+else
+FFMPEG_CONF_OPTS += --disable-avx2
+endif
+
 # Explicitly disable everything that doesn't match for ARM
 # FFMPEG "autodetects" by compiling an extended instruction via AS
 # This works on compilers that aren't built for generic by default
package/opencv/opencv.mk +2 -0
index 61f529e..ee84312 100644
@@ -77,6 +77,8 @@ OPENCV_CONF_OPTS += \
 	-DENABLE_SSE3=$(if $(BR2_X86_CPU_HAS_SSE3),ON,OFF)   \
 	-DENABLE_SSE41=$(if $(BR2_X86_CPU_HAS_SSE4),ON,OFF)  \
 	-DENABLE_SSE42=$(if $(BR2_X86_CPU_HAS_SSE42),ON,OFF) \
+	-DENABLE_AVX=$(if $(BR2_X86_CPU_HAS_AVX),ON,OFF) \
+	-DENABLE_AVX2=$(if $(BR2_X86_CPU_HAS_AVX2),ON,OFF) \
 	-DENABLE_SSSE3=$(if $(BR2_X86_CPU_HAS_SSSE3),ON,OFF)
 
 # Cuda stuff
Signature · 1 line
2.3.3
#9 lore raw

PATCH 1/3 arch: add corei7-avx

In reply to Steven Noonan

Dear Steven Noonan,

Quoted 4 lines · Steven Noonan
Signed-off-by Steven Noonan <[email protected]>
---
 arch/Config.in.x86 | 13 +++++++++++++
 1 file changed, 13 insertions(+)

All three patches applied, thanks a lot!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com