mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

PATCH New Vijay Rai 3 participants 6 messages Mar 25, 2015 – Apr 28, 2015

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Vijay Rai

author

2015-03-25 14:46 UTC #0 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM

Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU

Signed-off-by Vijay Rai <[email protected]>

Signed-off-by Priyanka Jain <[email protected]>

---
changes from v2:
- adds SGMII suport using CPLD
- removes extra endif
changes from v3:
- removes checkpatch error
changes from v4:
- wrong use of defined MACRO in eth.c file, adds macro properly
changes from v5:
- updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg
- update DDR settings

board/freescale/t104xrdb/MAINTAINERS | 8 ++++

 board/freescale/t104xrdb/README          |   75 ++++++++++++++++++++++++++++--
 board/freescale/t104xrdb/cpld.h          |    2 +
 board/freescale/t104xrdb/ddr.c           |    6 +++
 board/freescale/t104xrdb/ddr.h           |    9 +++-
 board/freescale/t104xrdb/eth.c           |   20 +++++++-
 board/freescale/t104xrdb/t1040d4_rcw.cfg |    7 +++
 board/freescale/t104xrdb/t1042d4_rcw.cfg |    7 +++
 board/freescale/t104xrdb/t104xrdb.c      |   21 +++++++++
 configs/T1040D4RDB_NAND_defconfig        |    5 ++
 configs/T1040D4RDB_SDCARD_defconfig      |    5 ++
 configs/T1040D4RDB_SPIFLASH_defconfig    |    5 ++
 configs/T1040D4RDB_defconfig             |    4 ++
 configs/T1042D4RDB_NAND_defconfig        |    5 ++
 configs/T1042D4RDB_SDCARD_defconfig      |    5 ++
 configs/T1042D4RDB_SPIFLASH_defconfig    |    5 ++
 configs/T1042D4RDB_defconfig             |    4 ++
 include/configs/T104xRDB.h               |   42 +++++++++++++----
 18 files changed, 220 insertions(+), 15 deletions(-)
 create mode 100644 board/freescale/t104xrdb/t1040d4_rcw.cfg
 create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg
 create mode 100644 configs/T1040D4RDB_NAND_defconfig
 create mode 100644 configs/T1040D4RDB_SDCARD_defconfig
 create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
 create mode 100644 configs/T1040D4RDB_defconfig
 create mode 100644 configs/T1042D4RDB_NAND_defconfig
 create mode 100644 configs/T1042D4RDB_SDCARD_defconfig
 create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
 create mode 100644 configs/T1042D4RDB_defconfig

board/freescale/t104xrdb/MAINTAINERS +8 -0

index 13d9be9..32e044f 100644
@@ -6,7 +6,13 @@ F:	include/configs/T104xRDB.h
 F:	configs/T1040RDB_defconfig
 F:	configs/T1040RDB_NAND_defconfig
 F:	configs/T1040RDB_SPIFLASH_defconfig
+F:	configs/T1040D4RDB_defconfig
+F:	configs/T1040D4RDB_NAND_defconfig
+F:	configs/T1040D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_defconfig
+F:	configs/T1042D4RDB_defconfig
+F:	configs/T1042D4RDB_NAND_defconfig
+F:	configs/T1042D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_PI_defconfig
 F:	configs/T1042RDB_PI_NAND_defconfig
 F:	configs/T1042RDB_PI_SPIFLASH_defconfig

@@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD
 #M:	-
 S:	Maintained
 F:	configs/T1040RDB_SDCARD_defconfig
+F:	configs/T1040D4RDB_SDCARD_defconfig
+F:	configs/T1042D4RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
 
 T1040RDB_SECURE_BOOT BOARD

board/freescale/t104xrdb/README +72 -3

102 lines not on this page · raw message

board/freescale/t104xrdb/cpld.h +2 -0

index 0da9a01..543ab53 100644
@@ -38,3 +38,5 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
 #define CPLD_WRITE(reg, value)\
 		cpld_write(offsetof(struct cpld_data, reg), value)
+#define MISC_CTL_SG_SEL		0x80
+#define MISC_CTL_AURORA_SEL	0x02

board/freescale/t104xrdb/ddr.c +6 -0

index e1148e5..3c4eabf 100644
@@ -91,8 +91,14 @@ found:
 	popts->zq_en = 1;
 
 	/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+		DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #if defined(CONFIG_DEEP_SLEEP)

board/freescale/t104xrdb/ddr.h +8 -1

index ab1c32d..58b7349 100644
@@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1600, 4, 4,     6, 0x07090A0d, 0x0D0f100a},
+#elif defined(CONFIG_SYS_FSL_DDR3)
 	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
 	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
 	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},

@@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = {
 	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
 	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
 	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+#else
+#error DDR type not defined
+#endif
 	{}
 };
 
+#endif
+
 static const struct board_specific_parameters *udimms[] = {
 	udimm0,
 };
-#endif

board/freescale/t104xrdb/eth.c +18 -2

index 7581a4cd..71d0457 100644
@@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis)
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 		case PHY_INTERFACE_MODE_SGMII:
-			/* T1040RDB only supports SGMII on DTSEC3 */
+			/* T1040RDB & T1040D4RDB only supports SGMII on
+			 * DTSEC3
+			 */
 			fm_info_set_phy_address(FM1_DTSEC3,
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;

@@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis)
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
+#ifdef CONFIG_T1042D4RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+			 *  & DTSEC3
+			 */
+			if (FM1_DTSEC1 == i)
+				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+			if (FM1_DTSEC2 == i)
+				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+#endif
 		case PHY_INTERFACE_MODE_RGMII:
 			if (FM1_DTSEC4 == i)
 				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;

board/freescale/t104xrdb/t1040d4_rcw.cfg new file +7 -0

new file mode 100644
index 0000000..c1034b3
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000

board/freescale/t104xrdb/t1042d4_rcw.cfg new file +7 -0

new file mode 100644
index 0000000..9e0ee27
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000

board/freescale/t104xrdb/t104xrdb.c +21 -0

index 9cd5e15..963cae4 100644
@@ -28,7 +28,11 @@ int checkboard(void)
 	struct cpu_type *cpu = gd->arch.cpu;
 	u8 sw;
 
+#ifdef CONFIG_T104XD4RDB
+	printf("Board: %sD4RDB\n", cpu->name);
+#else
 	printf("Board: %sRDB\n", cpu->name);
+#endif
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));

@@ -91,6 +95,23 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+	printf("SERDES Reference : 0x%X\n", srds_s1);
+
+	/* select SGMII*/
+	if (srds_s1 == 0x86)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL);
+
+	/* select SGMII and Aurora*/
+	if (srds_s1 == 0x8E)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
 	return 0;
 }

configs/T1040D4RDB_NAND_defconfig new file +5 -0

new file mode 100644
index 0000000..8212b34
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SDCARD_defconfig new file +5 -0

new file mode 100644
index 0000000..d45c60c
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SPIFLASH_defconfig new file +5 -0

new file mode 100644
index 0000000..d7ccacf
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_defconfig new file +4 -0

new file mode 100644
index 0000000..f9a23cf
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_NAND_defconfig new file +5 -0

new file mode 100644
index 0000000..2ab2b15
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SDCARD_defconfig new file +5 -0

new file mode 100644
index 0000000..daba6b7
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SPIFLASH_defconfig new file +5 -0

new file mode 100644
index 0000000..0aa5178
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_defconfig new file +4 -0

new file mode 100644
index 0000000..3802637
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

include/configs/T104xRDB.h +33 -9

101 lines not on this page · raw message

Signature · 1 line

1.7.9.5

York Sun

2015-04-13 17:18 UTC #1 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

Quoted 18 lines · Vijay Rai

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by Vijay Rai <[email protected]>
Signed-off-by Priyanka Jain <[email protected]>

Quoted 11 lines

---
changes from v2:
- adds SGMII suport using CPLD
- removes extra endif
changes from v3:
- removes checkpatch error
changes from v4:
- wrong use of defined MACRO in eth.c file, adds macro properly
changes from v5:
- updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg
- update DDR settings

This should be v6 in subject line.

York

York Sun

2015-04-16 19:14 UTC #2 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

In reply to Vijay Rai

On 03/25/2015 07:46 AM, Vijay Rai wrote:

<snip>

Quoted 82 lines

configs/T1040D4RDB_NAND_defconfig new file +5 -0

new file mode 100644
index 0000000..8212b34
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SDCARD_defconfig new file +5 -0

new file mode 100644
index 0000000..d45c60c
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SPIFLASH_defconfig new file +5 -0

new file mode 100644
index 0000000..d7ccacf
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_defconfig new file +4 -0

new file mode 100644
index 0000000..f9a23cf
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_NAND_defconfig new file +5 -0

new file mode 100644
index 0000000..2ab2b15
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SDCARD_defconfig new file +5 -0

new file mode 100644
index 0000000..daba6b7
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SPIFLASH_defconfig new file +5 -0

new file mode 100644
index 0000000..0aa5178
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_defconfig new file +0 -0

new file mode 100644
index 0000000..3802637

configs/T1042D4RDB_defconfig line 4

Quoted 4 lines

configs/T1042D4RDB_defconfig new file +4 -0

@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

Please do not use CONFIG_SYS_EXTRA_OPTIONS for new boards.

York

York Sun

2015-04-27 19:02 UTC #3 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

Quoted 5 lines · York Sun

On 03/25/2015 07:46 AM, Vijay Rai wrote:
<snip>

<snip>

Quoted 2 lines

Please do not use CONFIG_SYS_EXTRA_OPTIONS for new boards.

As Masahiro explained, it is too early to enforce CONFIG_SYS_EXTRA_OPTIONS. This patch is moved back into the queue.

York

Codrin Constantin Ciubotariu

2015-04-28 11:15 UTC #4 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

In reply to Vijay Rai

include/configs/T104xRDB.h line 738

Quoted 10 lines

#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)

include/configs/T104xRDB.h +6 -1

-#define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#endif

The PHY address for SGMII PHY connected to FM1 at DTSEC3 on T1040D4RDB should be 0x01, not 0x02 (CONFIG_SYS_SGMII1_PHY_ADDR).

Best regards,
Codrin

York Sun

2015-04-28 16:13 UTC #5 lore raw

PATCH 1/1 mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

Rijay,

Quoted 13 lines · On 04/28/2015 04:15 AM, Ciubotariu Codrin Constantin-B43658 wrote:

include/configs/T104xRDB.h line 738
Quoted 10 lines
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
include/configs/T104xRDB.h +6 -1
-#define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#endif
The PHY address for SGMII PHY connected to FM1 at DTSEC3 on T1040D4RDB should be 0x01, not 0x02 (CONFIG_SYS_SGMII1_PHY_ADDR).

Please check the PHY address. If you send a new patch, please rebase to the latest master. A change is needed in defconfig file.

York