cxgb4: add FCoE DDP and RSS

index 5e53327..210f04a 100644
@@ -818,15 +818,6 @@ struct cpl_pass_accept_req {
 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
 
-struct ulptx_idata {
-	__be32 cmd_more;
-	__be32 len;
-};
-
-#define ULPTX_NSGE_S    0
-#define ULPTX_NSGE_M    0xFFFF
-#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
-
 #define RX_DACK_MODE_S    29
 #define RX_DACK_MODE_M    0x3
 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)

index 30a2f56..7e2137d 100644
@@ -1054,6 +1054,11 @@ struct ulptx_sgl {
 	struct ulptx_sge_pair sge[0];
 };
 
+struct ulptx_idata {
+	__be32 cmd_more;
+	__be32 len;
+};
+
 #define ULPTX_NSGE_S    0
 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
 

index 1096026..342263b 100644
@@ -23,11 +23,6 @@
 #define CXGB4I_TX_HEADER_LEN \
 	(sizeof(struct fw_ofld_tx_data_wr) + sizeof(struct sge_opaque_hdr))
 
-struct ulptx_idata {
-	__be32 cmd_more;
-	__be32 len;
-};
-
 struct cpl_rx_data_ddp {
 	union opcode_tid ot;
 	__be16 urg;

index bf9258a..458c696 100644
@@ -40,18 +40,70 @@
 #define CXGB_FCOE_TXPKT_CSUM_START	28
 #define CXGB_FCOE_TXPKT_CSUM_END	8
 
+#define CXGB_FCOE_ATID		13
+#define CXGB_FCOE_GET_XID(x)	((x) & 0x3FF)
+
+#define CXGB_FCOE_SHIFT_PORTID	11
+#define CXGB_FCOE_MASK_PORTID	0x3
+#define CXGB_FCOE_GET_PORTID(x)	\
+	(((x) >> CXGB_FCOE_SHIFT_PORTID) & CXGB_FCOE_MASK_PORTID)
+
+/* # of sentinel invalid page pods at the end of a group of valid page pods */
+#define CXGB_FCOE_NUM_SENTINEL_PPODS	0
+
+#define CXGB_FCOE_PPOD_SIZE		sizeof(struct pagepod)
+
+#define CXGB_FCOE_MAX_XCHGS_PORT	1024	/* Per netdev */
+#define CXGB_FCOE_MAX_PAGE_CNT		((10485760) / PAGE_SIZE)
+
+/* ddp flags */
+enum {
+	CXGB_FCOE_DDP_ERROR     = (1 << 0),
+	CXGB_FCOE_DDP_TID_VALID = (1 << 1),
+};
+
+struct cxgb_fcoe_ddp {
+	u8 h_source[ETH_ALEN];
+	u8 h_dest[ETH_ALEN];
+	unsigned int sgc;
+	struct scatterlist *sgl;
+	int ddp_len;
+	unsigned int tid;
+	unsigned int nppods;
+	unsigned int npages;
+	unsigned int ppod_tag;
+	unsigned int first_pg_off;
+	unsigned int xfer_len;
+	u16 vlan_tci;
+	u16 xid;
+	u8 d_id[3];
+	u8 flags;
+	dma_addr_t *ppod_gl;
+};
+
 /* fcoe flags */
 enum {
 	CXGB_FCOE_ENABLED     = (1 << 0),
 };
 
 struct cxgb_fcoe {
-	u8	flags;
+	u8 flags;
+	struct completion *cmpl;
+	struct cxgb_fcoe_ddp ddp[CXGB_FCOE_MAX_XCHGS_PORT];
 };
 
 int cxgb_fcoe_enable(struct net_device *);
 int cxgb_fcoe_disable(struct net_device *);
 bool cxgb_fcoe_sof_eof_supported(struct adapter *, struct sk_buff *);
 
+void cxgb_fcoe_init_ddp(struct adapter *);
+void cxgb_fcoe_exit_ddp(struct adapter *);
+void cxgb_fcoe_cpl_act_open_rpl(struct adapter *, unsigned int,
+				unsigned int, unsigned int);
+int cxgb_fcoe_rx_handler(struct sge_rspq *, const __be64 *);
+void cxgb_fcoe_free_ppods(struct adapter *, unsigned int, unsigned int);
+int cxgb_fcoe_ddp_setup(struct net_device *, u16,
+			struct scatterlist *, unsigned int);
+int cxgb_fcoe_ddp_done(struct net_device *, u16);
 #endif /* CONFIG_CHELSIO_T4_FCOE */
 #endif /* __CXGB4_FCOE_H__ */

index 78ab4d4..412a740 100644
@@ -218,6 +218,13 @@ struct cxgb4_virt_res {                      /* virtualized HW resources */
 	struct cxgb4_range qp;
 	struct cxgb4_range cq;
 	struct cxgb4_range ocq;
+#ifdef CONFIG_CHELSIO_T4_FCOE
+	u8 *ppod_map;
+	u16 *tid2xid;
+	unsigned int toe_nppods;
+	unsigned int fcoe_nppods;
+	spinlock_t ppod_map_lock;	/* page pod map lock */
+#endif /* CONFIG_CHELSIO_T4_FCOE */
 };
 
 #define OCQ_WIN_OFFSET(pdev, vres) \

index 380b15c..133e776 100644
@@ -164,6 +164,35 @@ struct rsp_ctrl {
 #define QINTR_TIMER_IDX(x) ((x) << 1)
 #define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7)
 
+/* # of pages a pagepod can hold without needing another pagepod */
+#define PPOD_PAGES 4U
+
+struct pagepod {
+	__be64 vld_tid_pgsz_tag_color;
+	__be64 len_offset;
+	__be64 rsvd;
+	__be64 addr[PPOD_PAGES + 1];
+};
+
+#define PPOD_COLOR_S    0
+#define PPOD_COLOR_V(x) ((x) << PPOD_COLOR_S)
+
+#define PPOD_TAG_S    6
+#define PPOD_TAG_V(x) ((x) << PPOD_TAG_S)
+
+#define PPOD_TID_S    32
+#define PPOD_TID_V(x) ((__u64)(x) << PPOD_TID_S)
+
+#define PPOD_VALID_S    56
+#define PPOD_VALID_V(x) ((__u64)(x) << PPOD_VALID_S)
+#define PPOD_VALID_F    PPOD_VALID_V(1ULL)
+
+#define PPOD_LEN_S    32
+#define PPOD_LEN_V(x) ((__u64)(x) << PPOD_LEN_S)
+
+#define PPOD_OFST_S    0
+#define PPOD_OFST_V(x) ((x) << PPOD_OFST_S)
+
 /*
  * Flash layout.
  */

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90 lines not on this page · raw message

index 19b2dcf..28a8d36 100644
@@ -61,6 +61,9 @@
 #define SGE_TIMERREGS			6
 #define TIMERREG_COUNTER0_X		0
 
+/* Egress Context field values */
+#define IDXSIZE_UNIT_X			64
+
 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
  * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
  * offsets 8x and a Write Combining single 64-byte Egress Queue Unit

index 03fbfd1..0babf8e 100644
@@ -101,6 +101,7 @@ enum fw_wr_opcodes {
 	FW_RI_BIND_MW_WR               = 0x18,
 	FW_RI_FR_NSMR_WR               = 0x19,
 	FW_RI_INV_LSTAG_WR             = 0x1a,
+	FW_POFCOE_ULPTX_WR	       = 0x43,
 	FW_LASTC2E_WR                  = 0x70
 };
 

@@ -631,6 +632,12 @@ struct fw_eth_tx_pkt_vm_wr {
 	__be16 vlantci;
 };
 
+struct fw_pofcoe_ulptx_wr {
+	__be32 op_pkd;
+	__be32 equiq_to_len16;
+	__u64  cookie;
+};
+
 #define FW_CMD_MAX_TIMEOUT 10000
 
 /*

@@ -985,6 +992,8 @@ enum fw_caps_config_fcoe {
 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD	= 0x00000004,
+	FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
+	FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,
 };
 
 enum fw_memtype_cf {

index 524d110..8cc53f9 100644
@@ -247,6 +247,7 @@ struct tp_params {
 	 * places we store their offsets here, or a -1 if the field isn't
 	 * present.
 	 */
+	int fcoe_shift;
 	int vlan_shift;
 	int vnic_shift;
 	int port_shift;

641 lines not on this page · raw message

index 24e10ea..95e7527 100644
@@ -544,6 +544,23 @@ static void clear_filter(struct adapter *adap, struct filter_entry *f)
 	memset(f, 0, sizeof(*f));
 }
 
+#ifdef CONFIG_CHELSIO_T4_FCOE
+static void hash_filter_rpl(struct adapter *adap,
+			    const struct cpl_act_open_rpl *rpl)
+{
+	unsigned int tid = GET_TID(rpl);
+	unsigned int ftid = TID_TID_G(AOPEN_ATID_G(ntohl(rpl->atid_status)));
+	unsigned int status  = AOPEN_STATUS_G(ntohl(rpl->atid_status));
+
+	/* ATID is 14 bit value [0..13], MAX_ATIDS is 8192
+	 * ATID needs max 13 bits [0..12], using 13th bit in
+	 * ATID for FCoE CPL_ACT_OPEN_REQ.
+	 */
+	if (ftid & BIT(CXGB_FCOE_ATID))
+		cxgb_fcoe_cpl_act_open_rpl(adap, ftid, tid, status);
+}
+#endif /* CONFIG_CHELSIO_T4_FCOE */
+
 /* Handle a filter write/deletion reply.
  */
 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)

@@ -661,7 +678,15 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 		const struct cpl_set_tcb_rpl *p = (void *)rsp;
 
 		filter_rpl(q->adap, p);
-	} else
+	}
+#ifdef CONFIG_CHELSIO_T4_FCOE
+	else if (opcode == CPL_ACT_OPEN_RPL) {
+		const struct cpl_act_open_rpl *p = (void *)rsp;
+
+		hash_filter_rpl(q->adap, p);
+	}
+#endif /* CONFIG_CHELSIO_T4_FCOE */
+	else
 		dev_err(q->adap->pdev_dev,
 			"unexpected CPL %#x on FW event queue\n", opcode);
 out:

@@ -3010,6 +3035,8 @@ static const struct net_device_ops cxgb4_netdev_ops = {
 #ifdef CONFIG_CHELSIO_T4_FCOE
 	.ndo_fcoe_enable      = cxgb_fcoe_enable,
 	.ndo_fcoe_disable     = cxgb_fcoe_disable,
+	.ndo_fcoe_ddp_target  = cxgb_fcoe_ddp_setup,
+	.ndo_fcoe_ddp_done    = cxgb_fcoe_ddp_done,
 #endif /* CONFIG_CHELSIO_T4_FCOE */
 #ifdef CONFIG_NET_RX_BUSY_POLL
 	.ndo_busy_poll        = cxgb_busy_poll,

@@ -3845,6 +3872,10 @@ static int adap_init0(struct adapter *adap)
 		adap->vres.ddp.start = val[3];
 		adap->vres.ddp.size = val[4] - val[3] + 1;
 		adap->params.ofldq_wr_cred = val[5];
+#ifdef CONFIG_CHELSIO_T4_FCOE
+		if (ntohs(caps_cmd.fcoecaps) & FW_CAPS_CONFIG_POFCOE_TARGET)
+			cxgb_fcoe_init_ddp(adap);
+#endif /* CONFIG_CHELSIO_T4_FCOE */
 
 		adap->params.offload = 1;
 	}

@@ -3965,6 +3996,9 @@ bye:
 	kfree(adap->sge.txq_maperr);
 	if (ret != -ETIMEDOUT && ret != -EIO)
 		t4_fw_bye(adap, adap->mbox);
+#ifdef CONFIG_CHELSIO_T4_FCOE
+	cxgb_fcoe_exit_ddp(adap);
+#endif /* CONFIG_CHELSIO_T4_FCOE */
 	return ret;
 }
 

@@ -4757,6 +4791,9 @@ static void remove_one(struct pci_dev *pdev)
 		iounmap(adapter->regs);
 		if (!is_t4(adapter->params.chip))
 			iounmap(adapter->bar2);
+#ifdef CONFIG_CHELSIO_T4_FCOE
+		cxgb_fcoe_exit_ddp(adapter);
+#endif /* CONFIG_CHELSIO_T4_FCOE */
 		pci_disable_pcie_error_reporting(pdev);
 		if ((adapter->flags & DEV_ENABLED)) {
 			pci_disable_device(pdev);

361 lines not on this page · raw message

index 5959e3a..bcb0567 100644
@@ -5303,6 +5303,7 @@ int t4_init_tp_params(struct adapter *adap)
 	 * shift positions of several elements of the Compressed Filter Tuple
 	 * for this adapter which we need frequently ...
 	 */
+	adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
 	adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
 	adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
 	adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);

index 95e7527..606aa5a 100644
@@ -910,6 +910,9 @@ int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 static int setup_rss(struct adapter *adap)
 {
 	int i, err;
+#ifdef CONFIG_CHELSIO_T4_FCOE
+	u32 rss_config;
+#endif
 
 	for_each_port(adap, i) {
 		const struct port_info *pi = adap2pinfo(adap, i);

@@ -918,6 +921,11 @@ static int setup_rss(struct adapter *adap)
 		if (err)
 			return err;
 	}
+#ifdef CONFIG_CHELSIO_T4_FCOE
+	rss_config = t4_read_reg(adap, TP_RSS_CONFIG_A);
+	rss_config |= TNLFCOEEN_F | TNLFCOEMODE_F;
+	t4_write_reg(adap, TP_RSS_CONFIG_A, rss_config);
+#endif
 	return 0;
 }
 

index 326674b..3e10c99 100644
@@ -1856,6 +1856,14 @@
 #define DISABLE_V(x) ((x) << DISABLE_S)
 #define DISABLE_F    DISABLE_V(1U)
 
+#define TNLFCOEMODE_S    23
+#define TNLFCOEMODE_V(x) ((x) << TNLFCOEMODE_S)
+#define TNLFCOEMODE_F    TNLFCOEMODE_V(1U)
+
+#define TNLFCOEEN_S    21
+#define TNLFCOEEN_V(x) ((x) << TNLFCOEEN_S)
+#define TNLFCOEEN_F    TNLFCOEEN_V(1U)
+
 #define TP_RSS_CONFIG_TNL_A 0x7df4
 
 #define MASKSIZE_S    28