Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC Tang Yuantian <[email protected]>

CC York Sun <[email protected]>

CC Steve Rae <[email protected]>

CC Andre Przywara <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC,

thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC Tang Yuantian <[email protected]>

CC York Sun <[email protected]>

CC Steve Rae <[email protected]>

CC Andre Przywara <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

---
 arch/arm/cpu/armv7/Makefile             | 2 +-
 arch/arm/cpu/armv7/ls102xa/cpu.c        | 2 +-
 arch/arm/cpu/armv7/virt-dt.c            | 2 +-
 arch/arm/cpu/u-boot.lds                 | 2 +-
 arch/arm/include/asm/armv7.h            | 4 ++--
 arch/arm/lib/bootm-fdt.c                | 2 +-
 arch/arm/lib/bootm.c                    | 6 +++---
 board/armltd/vexpress/vexpress_common.c | 2 +-
 board/broadcom/bcm_ep/board.c           | 2 +-
 board/freescale/common/arm_sleep.c      | 2 +-
 10 files changed, 13 insertions(+), 13 deletions(-)

arch/arm/cpu/armv7/Makefile +1 -1

index 21fc03b..fbd0bf3 100644
@@ -18,7 +18,7 @@ obj-y	+= lowlevel_init.o
 endif
 endif
 
-ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+ifneq ($(CONFIG_ARMV7_NONSEC),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
 obj-y	+= virt-dt.o

arch/arm/cpu/armv7/ls102xa/cpu.c +1 -1

index 1a640bb..75f0d8c 100644
@@ -329,7 +329,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {

arch/arm/cpu/armv7/virt-dt.c +0 -0

index 9408e33..caaaaab 100644

arch/arm/cpu/armv7/virt-dt.c +0 -0

 	if (!armv7_boot_nonsec())
 		return 0;
 #endif

arch/arm/cpu/u-boot.lds +1 -1

index 7336162..03cd9f6 100644
@@ -25,7 +25,7 @@ SECTIONS
 		*(.text*)
 	}
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
+#ifdef CONFIG_ARMV7_NONSEC
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE

arch/arm/include/asm/armv7.h +2 -2

index 58d8b16..2bb1253 100644
@@ -121,7 +121,7 @@ void v7_outer_cache_inval_all(void);
 void v7_outer_cache_flush_range(u32 start, u32 end);
 void v7_outer_cache_inval_range(u32 start, u32 end);
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 
 int armv7_init_nonsec(void);
 bool armv7_boot_nonsec(void);

@@ -135,7 +135,7 @@ void _smp_pen(void);
 extern char __secure_start[];
 extern char __secure_end[];
 
-#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+#endif /* CONFIG_ARMV7_NONSEC */
 
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 				 u32 cpu_rev_comb, u32 cpu_variant,

arch/arm/lib/bootm-fdt.c +1 -1

index 665a3bc..49ba691 100644
@@ -34,7 +34,7 @@ int arch_fixup_fdt(void *blob)
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 	if (ret)
 		return ret;
 

arch/arm/lib/bootm.c +3 -3

index b1bff8c..ee56d74 100644
@@ -26,7 +26,7 @@
 #include <bootm.h>
 #include <vxworks.h>
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 #include <asm/armv7.h>
 #endif
 

@@ -238,7 +238,7 @@ static void boot_prep_linux(bootm_headers_t *images)
 	}
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 bool armv7_boot_nonsec(void)
 {
 	char *s = getenv("bootm_boot_mode");

@@ -305,7 +305,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 		r2 = gd->bd->bi_boot_params;
 
 	if (!fake) {
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 		if (armv7_boot_nonsec()) {
 			armv7_init_nonsec();
 			secure_ram_addr(_do_nonsec_entry)(kernel_entry,

board/armltd/vexpress/vexpress_common.c +1 -1

index cb2de2f..d3b3b31 100644
@@ -181,7 +181,7 @@ ulong get_board_rev(void){
 	return readl((u32 *)SYS_ID);
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Setting the address at which secondary cores start from.
  * Versatile Express uses one address for all cores, so ignore corenr
  */

board/broadcom/bcm_ep/board.c +1 -1

index 6a70a2e..eaad0b3 100644
@@ -54,7 +54,7 @@ int board_early_init_f(void)
 	return status;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
 }

board/freescale/common/arm_sleep.c +1 -1

index 8edf878..30d9c7b 100644
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#ifndef CONFIG_ARMV7_NONSEC
 #error " Deep sleep needs non-secure mode support. "
 #else
 #include <asm/secure.h>

On Tue, 21 Apr 2015 07:18:24 +0200
Jan Kiszka <[email protected]> wrote:

Hi Jan,

Quoted 1 line

CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC,

Is this Kconfig rule always enforced these days? Or can one get away without it by using stuff from include/configs/*.h?

Quoted 4 lines

thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

Shouldn't this be also modelled in Kconfig then?

...

Quoted 50 lines

CC Tang Yuantian <[email protected]>

CC York Sun <[email protected]>

CC Steve Rae <[email protected]>

CC Andre Przywara <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

---
 arch/arm/cpu/armv7/Makefile             | 2 +-
 arch/arm/cpu/armv7/ls102xa/cpu.c        | 2 +-
 arch/arm/cpu/armv7/virt-dt.c            | 2 +-
 arch/arm/cpu/u-boot.lds                 | 2 +-
 arch/arm/include/asm/armv7.h            | 4 ++--
 arch/arm/lib/bootm-fdt.c                | 2 +-
 arch/arm/lib/bootm.c                    | 6 +++---
 board/armltd/vexpress/vexpress_common.c | 2 +-
 board/broadcom/bcm_ep/board.c           | 2 +-
 board/freescale/common/arm_sleep.c      | 2 +-
 10 files changed, 13 insertions(+), 13 deletions(-)

arch/arm/cpu/armv7/Makefile +1 -1

index 21fc03b..fbd0bf3 100644
@@ -18,7 +18,7 @@ obj-y	+= lowlevel_init.o
 endif
 endif
 
-ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+ifneq ($(CONFIG_ARMV7_NONSEC),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
 obj-y	+= virt-dt.o

arch/arm/cpu/armv7/ls102xa/cpu.c +1 -1

index 1a640bb..75f0d8c 100644
@@ -329,7 +329,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {

arch/arm/cpu/armv7/virt-dt.c +0 -0

index 9408e33..caaaaab 100644
@@ -90,7 +90,7 @@ static int fdt_psci(void *fdt)
 

arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 93

Quoted 4 lines

arch/arm/cpu/armv7/virt-dt.c +1 -1

 int psci_update_dt(void *fdt)
 {
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC

This is redundant now, isn't it? We compile this file only if CONFIG_ARMV7_NONSEC is defined (see above).

The rest of the patch looks OK to me.

Cheers,
Andre.

-----Original Message-----
From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
Sent: Tuesday, April 21, 2015 1:19 PM
To: U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control.

CC Marc Zyngier <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Thierry Reding <[email protected]>

Tested-by Thierry Reding <[email protected]>

Tested-by Ian Campbell <[email protected]>

---
 arch/arm/cpu/armv7/psci.S       | 11 +++++------
 arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
 2 files changed, 11 insertions(+), 9 deletions(-)

arch/arm/cpu/armv7/psci.S index renamed from arch/arm/cpu/armv7/psci.S +0 -0

18d85c4..87c0c0b 100644

arch/arm/cpu/armv7/psci.S +5 -6

@@ -17,6 +17,7 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/macro.h>
 #include <asm/psci.h>
 
 	.pushsection ._secure.text, "ax"

@@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
 	add	r5, r5, #0x2000			@ Skip two pages
 	lsr	r5, r5, #12			@ Align to start of page
 	lsl	r5, r5, #12
+	sub	r5, r5, #4			@ reserve 1 word for target PC
 	sub	r0, r5, r0			@ here's our stack!
 
 	bx	lr

@@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
 
 	bl	_nonsec_init
 
-	adr	r0, _psci_target_pc
-	ldr	r0, [r0]
+	bl	psci_get_cpu_id			@ CPU ID => r0
+	bl	psci_get_cpu_stack_top		@ stack top => r0
+	ldr	r0, [r0]			@ target PC at stack top
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
-.globl _psci_target_pc
-_psci_target_pc:
-	.word	0
-
 	.popsection

arch/arm/cpu/armv7/sunxi/psci.S +0 -0

index dd583b2..7ec0500 100644

Quoted 67 lines

-----Original Message-----
From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
Sent: Tuesday, April 21, 2015 1:19 PM
To: U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control.

CC Marc Zyngier <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Thierry Reding <[email protected]>

Tested-by Thierry Reding <[email protected]>

Tested-by Ian Campbell <[email protected]>

---
 arch/arm/cpu/armv7/psci.S       | 11 +++++------
 arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
 2 files changed, 11 insertions(+), 9 deletions(-)

arch/arm/cpu/armv7/psci.S index renamed from arch/arm/cpu/armv7/psci.S +0 -0

18d85c4..87c0c0b 100644

arch/arm/cpu/armv7/psci.S +5 -6

@@ -17,6 +17,7 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/macro.h>
 #include <asm/psci.h>
 
 	.pushsection ._secure.text, "ax"

@@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
 	add	r5, r5, #0x2000			@ Skip two pages
 	lsr	r5, r5, #12			@ Align to start of page
 	lsl	r5, r5, #12
+	sub	r5, r5, #4			@ reserve 1 word for target PC
 	sub	r0, r5, r0			@ here's our stack!
 
 	bx	lr

@@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
 
 	bl	_nonsec_init
 
-	adr	r0, _psci_target_pc
-	ldr	r0, [r0]
+	bl	psci_get_cpu_id			@ CPU ID => r0
+	bl	psci_get_cpu_stack_top		@ stack top => r0
+	ldr	r0, [r0]			@ target PC at stack top
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
-.globl _psci_target_pc
-_psci_target_pc:
-	.word	0
-
 	.popsection

arch/arm/cpu/armv7/sunxi/psci.S +0 -0

index dd583b2..7ec0500 100644

arch/arm/cpu/armv7/sunxi/psci.S out: mcr p15, 0, r7, c1, c1, 0 · line 146

Quoted 10 lines

arch/arm/cpu/armv7/sunxi/psci.S +5 -2

@@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
 	@ r2 = target PC
 .globl	psci_cpu_on
 psci_cpu_on:
-	ldr	r0, =_psci_target_pc
-	str	r2, [r0]
+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
+	str	r2, [r0]		@ store target PC at stack top

Base on target PC will be saved in stack. The cpu(r1) should be mask firstly. Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1 or ...). If not, the stack address is incorrect.

When I develop LS1021a PSCI code, I found this issue. So I think sunxi also has this issue.

-----Original Message-----
From: Jan Kiszka [mailto:jan.kiszka at siemens.com]
Sent: Wednesday, May 13, 2015 3:31 PM
To: Wang Dongsheng-B40534; U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
Subject: Re: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

Quoted 74 lines · Wang Dongsheng

Quoted 74 lines

-----Original Message-----
From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
Sent: Tuesday, April 21, 2015 1:19 PM
To: U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control.

CC Marc Zyngier <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Thierry Reding <[email protected]>

Tested-by Thierry Reding <[email protected]>

Tested-by Ian Campbell <[email protected]>

---
 arch/arm/cpu/armv7/psci.S       | 11 +++++------
 arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
 2 files changed, 11 insertions(+), 9 deletions(-)

arch/arm/cpu/armv7/psci.S +5 -6

index 18d85c4..87c0c0b 100644
@@ -17,6 +17,7 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/macro.h>
 #include <asm/psci.h>
 
 	.pushsection ._secure.text, "ax"

@@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
 	add	r5, r5, #0x2000			@ Skip two pages
 	lsr	r5, r5, #12			@ Align to start of page
 	lsl	r5, r5, #12
+	sub	r5, r5, #4			@ reserve 1 word for target PC
 	sub	r0, r5, r0			@ here's our stack!
 
 	bx	lr

@@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
 
 	bl	_nonsec_init
 
-	adr	r0, _psci_target_pc
-	ldr	r0, [r0]
+	bl	psci_get_cpu_id			@ CPU ID => r0
+	bl	psci_get_cpu_stack_top		@ stack top => r0
+	ldr	r0, [r0]			@ target PC at stack top
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
-.globl _psci_target_pc
-_psci_target_pc:
-	.word	0
-
 	.popsection

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/sunxi/psci.S index dd583b2..7ec0500 100644

arch/arm/cpu/armv7/sunxi/psci.S +0 -2

@@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
 	@ r2 = target PC
 .globl	psci_cpu_on
 psci_cpu_on:
-	ldr	r0, =_psci_target_pc
-	str	r2, [r0]

Quoted 8 lines

arch/arm/cpu/armv7/sunxi/psci.S out: mcr p15, 0, r7, c1, c1, 0 · line 146

Quoted 5 lines

arch/arm/cpu/armv7/sunxi/psci.S +5 -0

+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
+	str	r2, [r0]		@ store target PC at stack top

Base on target PC will be saved in stack. The cpu(r1) should be mask firstly. Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1

or ...).

Quoted 4 lines

If not, the stack address is incorrect.

When I develop LS1021a PSCI code, I found this issue. So I think sunxi also has this issue.

IIRC, sunxi has no clusters != 0 so far, but you are right conceptually.

We already mask elsewhere in that function, so the instruction should simply be moved up here.

From: Ian Campbell <[email protected]>

The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. See next patch.

Signed-off-by Ian Campbell <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Thierry Reding <[email protected]>

Tested-by Thierry Reding <[email protected]>

Tested-by Ian Campbell <[email protected]>

---
 arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
 include/configs/jetson-tk1.h         | 5 +++++
 2 files changed, 7 insertions(+)

arch/arm/mach-tegra/tegra124/Kconfig +2 -0

index 88f627c..5114299 100644
@@ -5,6 +5,8 @@ choice
 
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
+	select CPU_V7_HAS_NONSEC if !SPL_BUILD
+	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chrombook"

include/configs/jetson-tk1.h +5 -0

index 8c016b7..aeafbd5 100644
@@ -79,4 +79,9 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
+#define CONFIG_ARMV7_PSCI			1
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
 #endif /* __CONFIG_H */

Quoted 5 lines · Jan Kiszka

From: Ian Campbell <[email protected]>

The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. See next patch.

Next patch, but this is the last one? Was it reordered earlier in the series or is it not yet included here?

Quoted 40 lines

Signed-off-by Ian Campbell <[email protected]>

Signed-off-by Jan Kiszka <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Thierry Reding <[email protected]>

Tested-by Thierry Reding <[email protected]>

Tested-by Ian Campbell <[email protected]>

---
 arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
 include/configs/jetson-tk1.h         | 5 +++++
 2 files changed, 7 insertions(+)

arch/arm/mach-tegra/tegra124/Kconfig +2 -0

index 88f627c..5114299 100644
@@ -5,6 +5,8 @@ choice
 
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
+	select CPU_V7_HAS_NONSEC if !SPL_BUILD
+	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chrombook"

include/configs/jetson-tk1.h +5 -0

index 8c016b7..aeafbd5 100644
@@ -79,4 +79,9 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
+#define CONFIG_ARMV7_PSCI			1
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
 #endif /* __CONFIG_H */

Changes in v7:
- rebased over master
- fixed issue that prevented secure boot with all cores
=> replace ap_pm_init with psci_board_init hook
- enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with default config of current Linux
- add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI

Note that I've removed reviewed and tested tags from modified patches.

Changes in v7:
- rebased over master
- fixed issue that prevented secure boot with all cores
=> replace ap_pm_init with psci_board_init hook
- enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with default config of current Linux
- add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI

Note that I've removed reviewed and tested tags from modified patches.

-----Original Message-----
From: Jan Kiszka [mailto:jan.kiszka at siemens.com]
Sent: Thursday, May 07, 2015 11:01 PM
To: U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Steve Rae; Andre Przywara; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding; York Sun
Subject: Re: [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

Quoted 5 lines · Jan Kiszka

Changes in v7:
- rebased over master
- fixed issue that prevented secure boot with all cores => replace ap_pm_init with psci_board_init hook
- enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems

with

Quoted 5 lines

default config of current Linux
- add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI

Note that I've removed reviewed and tested tags from modified patches.

Tom, there were only trivial remarks regarding this series, and it still applies on master. Do you plan to merge it? Or should I resend, addressing them?

Jan

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