arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

RFC PATCH New Nikolay Dimitrov 5 participants 10 messages Apr 16, 2015 – Apr 23, 2015 Arm (32-bit)

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Nikolay Dimitrov

author

2015-04-16 22:36 UTC #0 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.

Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.

Signed-off-by Nikolay Dimitrov <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Tim Harvey <[email protected]>

Cc Eric Nelson <[email protected]>

---
 arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +20 -5

index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 	u8 coladdr;
 	int clkper; /* clock period in picoseconds */
-	int clock; /* clock freq in mHz */
+	int clock; /* clock freq in MHz */
 	int cs;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;

@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 #endif
 
-	/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+	/* Limit mem_speed for MX6D/MX6Q */
 	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-		clock = 528;
+		if (ddr3_cfg->mem_speed > 1066)
+			ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+
 		tcwl = 4;
 	}
-	/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+	/* Limit mem_speed for MX6S/MX6DL */
 	else {
-		clock = 400;
+		if (ddr3_cfg->mem_speed > 800)
+			ddr3_cfg->mem_speed = 800;  /* 800 MT/s */
+
 		tcwl = 3;
 	}
+
+	clock = ddr3_cfg->mem_speed / 2;
+	/*
+	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
+	 * up to 528 MHz, so reduce the clock to fit chip specs
+	 */
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+		if (clock > 528)
+			clock = 528; /* 528 MHz */
+	}
+
 	clkper = (1000 * 1000) / clock; /* pico seconds */
 	todtlon = tcwl;
 	taxpd = tcwl;

Signature · 1 line

1.7.10.4

Otavio Salvador

2015-04-17 00:53 UTC #1 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

Quoted 8 lines · Nikolay Dimitrov

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.

Quoted 5 lines

Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>

It does looks way nicer. It is much easier to understand what is going behind the scenes.

Acked-by Otavio Salvador <[email protected]>

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Tim Harvey

2015-04-21 04:17 UTC #2 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

In reply to Nikolay Dimitrov

Quoted 8 lines · Nikolay Dimitrov

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.

Quoted 5 lines

Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>

Nikolay,

Makes sense to me.

Acked-by Tim Harvey <[email protected]>

Igor Grinberg

2015-04-22 06:08 UTC #3 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

In reply to Nikolay Dimitrov

Quoted 8 lines · Nikolay Dimitrov

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.

Quoted 5 lines

Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>

Acked-by Igor Grinberg <[email protected]>

Signature · 2 lines

Regards,
Igor.

Stefano Babic

2015-04-22 12:12 UTC #4 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

In reply to Nikolay Dimitrov

Hi Nikolay,

Quoted 57 lines · Nikolay Dimitrov

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.

Signed-off-by Nikolay Dimitrov <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Tim Harvey <[email protected]>

Cc Eric Nelson <[email protected]>

---
 arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +13 -5

index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 	u8 coladdr;
 	int clkper; /* clock period in picoseconds */
-	int clock; /* clock freq in mHz */
+	int clock; /* clock freq in MHz */
 	int cs;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;

@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 #endif
 
-	/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+	/* Limit mem_speed for MX6D/MX6Q */
 	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-		clock = 528;
+		if (ddr3_cfg->mem_speed > 1066)
+			ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+
 		tcwl = 4;
 	}
-	/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+	/* Limit mem_speed for MX6S/MX6DL */
 	else {
-		clock = 400;
+		if (ddr3_cfg->mem_speed > 800)
+			ddr3_cfg->mem_speed = 800;  /* 800 MT/s */
+
 		tcwl = 3;
 	}
+
+	clock = ddr3_cfg->mem_speed / 2;
+	/*
+	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports

arch/arm/cpu/armv7/mx6/ddr.c void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 303

Quoted 10 lines

arch/arm/cpu/armv7/mx6/ddr.c +7 -0

+	 * up to 528 MHz, so reduce the clock to fit chip specs
+	 */
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+		if (clock > 528)
+			clock = 528; /* 528 MHz */
+	}
+
 	clkper = (1000 * 1000) / clock; /* pico seconds */
 	todtlon = tcwl;
 	taxpd = tcwl;

Well done. I think we can forget the RFC of the title and apply it.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Nikolay Dimitrov

author

2015-04-22 12:22 UTC #5 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

Hi Stefano,

Quoted 64 lines · Stefano Babic

Hi Nikolay,

Quoted 61 lines · Nikolay Dimitrov

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed.

Signed-off-by Nikolay Dimitrov <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Tim Harvey <[email protected]>

Cc Eric Nelson <[email protected]>

---
  arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
  1 file changed, 20 insertions(+), 5 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +18 -5

index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  	u8 coladdr;
  	int clkper; /* clock period in picoseconds */
-	int clock; /* clock freq in mHz */
+	int clock; /* clock freq in MHz */
  	int cs;
 
  	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;

@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  #endif
 
-	/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+	/* Limit mem_speed for MX6D/MX6Q */
  	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-		clock = 528;
+		if (ddr3_cfg->mem_speed > 1066)
+			ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+
  		tcwl = 4;
  	}
-	/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+	/* Limit mem_speed for MX6S/MX6DL */
  	else {
-		clock = 400;
+		if (ddr3_cfg->mem_speed > 800)
+			ddr3_cfg->mem_speed = 800;  /* 800 MT/s */
+
  		tcwl = 3;
  	}
+
+	clock = ddr3_cfg->mem_speed / 2;
+	/*
+	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
+	 * up to 528 MHz, so reduce the clock to fit chip specs
+	 */
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+		if (clock > 528)
+			clock = 528; /* 528 MHz */

Quoted 8 lines

arch/arm/cpu/armv7/mx6/ddr.c void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 303
Quoted 6 lines
arch/arm/cpu/armv7/mx6/ddr.c +2 -0
+	}
+
  	clkper = (1000 * 1000) / clock; /* pico seconds */
  	todtlon = tcwl;
  	taxpd = tcwl;
Well done. I think we can forget the RFC of the title and apply it.

Do you need me to reword the commit message?

Regards,
Nikolay

Stefano Babic

2015-04-22 12:47 UTC #6 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

Quoted 82 lines · Nikolay Dimitrov

Hi Stefano,
Quoted 70 lines · Stefano Babic
Hi Nikolay,
Quoted 67 lines · Nikolay Dimitrov
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.
Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>
---
  arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
  1 file changed, 20 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
      u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
      u8 coladdr;
      int clkper; /* clock period in picoseconds */
-    int clock; /* clock freq in mHz */
+    int clock; /* clock freq in MHz */
      int cs;
 
      mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
arch/arm/cpu/armv7/mx6/ddr.c +12 -4
@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
      mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  #endif
 
-    /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+    /* Limit mem_speed for MX6D/MX6Q */
      if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-        clock = 528;
+        if (ddr3_cfg->mem_speed > 1066)
+            ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+
          tcwl = 4;
      }
-    /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+    /* Limit mem_speed for MX6S/MX6DL */
      else {
-        clock = 400;
+        if (ddr3_cfg->mem_speed > 800)
+            ddr3_cfg->mem_speed = 800;  /* 800 MT/s */
+
          tcwl = 3;
      }
+
+    clock = ddr3_cfg->mem_speed / 2;
+    /*
+     * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but
MX6D/Q supports
arch/arm/cpu/armv7/mx6/ddr.c +5 -0
+     * up to 528 MHz, so reduce the clock to fit chip specs
+     */
+    if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+        if (clock > 528)
+            clock = 528; /* 528 MHz */
Quoted 8 lines
arch/arm/cpu/armv7/mx6/ddr.c void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 303
Quoted 6 lines
arch/arm/cpu/armv7/mx6/ddr.c +2 -0
+    }
+
      clkper = (1000 * 1000) / clock; /* pico seconds */
      todtlon = tcwl;
      taxpd = tcwl;
Well done. I think we can forget the RFC of the title and apply it.

Quoted 1 line

Do you need me to reword the commit message?

No, I check myself, thanks.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2015-04-22 14:02 UTC #7 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

In reply to Nikolay Dimitrov

Hi Nikolay,

Quoted 45 lines · Nikolay Dimitrov

Hi Stefano,
Quoted 42 lines · Stefano Babic
Hi Nikolay,
Quoted 39 lines · Nikolay Dimitrov
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.
Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>
---
  arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
  1 file changed, 20 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
      u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
      u8 coladdr;
      int clkper; /* clock period in picoseconds */
-    int clock; /* clock freq in mHz */
+    int clock; /* clock freq in MHz */
      int cs;
 
      mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
arch/arm/cpu/armv7/mx6/ddr.c +0 -0
@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
      mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  #endif
 

Quoted 7 lines

arch/arm/cpu/armv7/mx6/ddr.c void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 280

Quoted 7 lines

arch/arm/cpu/armv7/mx6/ddr.c +4 -2

-    /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+    /* Limit mem_speed for MX6D/MX6Q */
      if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-        clock = 528;
+        if (ddr3_cfg->mem_speed > 1066)
+            ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+

Sorry, but there is an issue. Parameters are const struct *, and you are setting value here.

By testing I get on most mx6 boards:

+arch/arm/cpu/armv7/mx6/ddr.c: In function 'mx6_dram_cfg':
+arch/arm/cpu/armv7/mx6/ddr.c:279:4: error: assignment of member 'mem_speed' in read-only object +arch/arm/cpu/armv7/mx6/ddr.c:286:4: error: assignment of member 'mem_speed' in read-only object
+make[4]: *** [spl/arch/arm/cpu/armv7/mx6/ddr.o] Error 1

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Nikolay Dimitrov

author

2015-04-23 14:26 UTC #8 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

Hi Stefano,

Quoted 63 lines · Stefano Babic

Hi Nikolay,
Quoted 45 lines · Nikolay Dimitrov
Hi Stefano,
Quoted 42 lines · Stefano Babic
Hi Nikolay,
Quoted 39 lines · Nikolay Dimitrov
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations.
Signed-off-by Nikolay Dimitrov <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>
---
   arch/arm/cpu/armv7/mx6/ddr.c |   25 ++++++++++++++++++++-----
   1 file changed, 20 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
index fef2231..9daa180 100644
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
       u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
       u8 coladdr;
       int clkper; /* clock period in picoseconds */
-    int clock; /* clock freq in mHz */
+    int clock; /* clock freq in MHz */
       int cs;
 
       mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
arch/arm/cpu/armv7/mx6/ddr.c +0 -0
@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
       mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
   #endif
 
Quoted 7 lines
Quoted 7 lines
arch/arm/cpu/armv7/mx6/ddr.c void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 280
Quoted 7 lines
arch/arm/cpu/armv7/mx6/ddr.c +4 -2
-    /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+    /* Limit mem_speed for MX6D/MX6Q */
       if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-        clock = 528;
+        if (ddr3_cfg->mem_speed > 1066)
+            ddr3_cfg->mem_speed = 1066; /* 1066 MT/s */
+
Sorry, but there is an issue. Parameters are const struct *, and you are setting value here.
By testing I get on most mx6 boards:
(quoted diff) +2 -0
+arch/arm/cpu/armv7/mx6/ddr.c: In function 'mx6_dram_cfg':
+arch/arm/cpu/armv7/mx6/ddr.c:279:4: error: assignment of member

Quoted 4 lines

'mem_speed' in read-only object +arch/arm/cpu/armv7/mx6/ddr.c:286:4: error: assignment of member 'mem_speed' in read-only object
+make[4]: *** [spl/arch/arm/cpu/armv7/mx6/ddr.o] Error 1

Sorry for the stupid mistake, I've already sent v2.

Regards,
Nikolay

Stefano Babic

2015-04-23 14:28 UTC #9 lore raw

RFC PATCH 1/1 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

Hi Nikolay,

Quoted 9 lines · Nikolay Dimitrov

Quoted 7 lines
(quoted diff) +2 -0
+arch/arm/cpu/armv7/mx6/ddr.c: In function 'mx6_dram_cfg':
+arch/arm/cpu/armv7/mx6/ddr.c:279:4: error: assignment of member
'mem_speed' in read-only object +arch/arm/cpu/armv7/mx6/ddr.c:286:4: error: assignment of member 'mem_speed' in read-only object
+make[4]: *** [spl/arch/arm/cpu/armv7/mx6/ddr.o] Error 1
Sorry for the stupid mistake, I've already sent v2.

No probblem at all, I have seen it and I'll pick it up soon !

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================