Revert "spi: add config option to enable the WP pin function on st micron flashes"

PATCH New Jagannadha Sutradharudu Teki 2 participants 9 messages Dec 18, 2014 – Apr 23, 2015 Memory technology devices (MTD)

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Jagannadha Sutradharudu Teki

author

2014-12-18 13:51 UTC #0 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.

Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.

Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>

Cc Heiko Schocher <[email protected]>

---
 README                        | 11 -----------
 drivers/mtd/spi/sf_internal.h |  4 ----
 drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
 3 files changed, 45 deletions(-)

README +0 ~~-11~~

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
 		memories can be connected with a given cs line.
 		currently Xilinx Zynq qspi support these type of connections.
 
-		CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-		enable the W#/Vpp signal to disable writing to the status
-		register on ST MICRON flashes like the N25Q128.
-		The status register write enable/disable bit, combined with
-		the W#/VPP signal provides hardware data protection for the
-		device as follows: When the enable/disable bit is set to 1,
-		and the W#/VPP signal is driven LOW, the status register
-		nonvolatile bits become read-only and the WRITE STATUS REGISTER
-		operation will not execute. The only way to exit this
-		hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
 		CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
 #define STATUS_QEB_MXIC		(1 << 6)
 #define STATUS_PEC			(1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD			(1 << 7) /* SR write protect */
-#endif
-
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)
 #define SPI_FLASH_PAGE_ERASE_TIMEOUT		(5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-30~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-	u8 status;
-	int ret;
-
-	ret = spi_flash_cmd_read_status(flash, &status);
-	if (ret < 0)
-		return ret;
-
-	ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-	if (ret < 0)
-		return ret;
-
-	ret = spi_flash_cmd_write_disable(flash);
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-	return 0;
-}
-#endif
-
 /**
  * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
  *

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
 		puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
 	}
 #endif
-	if (spi_enable_wp_pin(flash))
-		puts("Enable WP pin failed\n");
 
 	/* Release spi bus */
 	spi_release_bus(spi);

Signature · 1 line

1.9.1

Jagan Teki

author

2014-12-22 08:58 UTC #1 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Quoted 99 lines · Jagannadha Sutradharudu Teki

This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.

Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.

Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>

Cc Heiko Schocher <[email protected]>

---
 README                        | 11 -----------
 drivers/mtd/spi/sf_internal.h |  4 ----
 drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
 3 files changed, 45 deletions(-)

README +0 ~~-11~~

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                currently Xilinx Zynq qspi support these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
                CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
 #define STATUS_QEB_MXIC                (1 << 6)
 #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
 #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-31~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
 /**
  * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
  *

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
                puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
        }
 #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");
 
        /* Release spi bus */
        spi_release_bus(spi);
--

Quoted 2 lines

1.9.1

Ping!

thanks!

Signature · 1 line

Jagan.

Heiko Schocher

2014-12-23 06:34 UTC #2 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Hello Jagan,

Am 22.12.2014 09:58, schrieb Jagan Teki:

Quoted 7 lines

Quoted 5 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.

Quoted 7 lines

Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
  README                        | 11 -----------
  drivers/mtd/spi/sf_internal.h |  4 ----
  drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
  3 files changed, 45 deletions(-)

I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.

bye,
Heiko

BTW: What is with the patchset:

[U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands
http://lists.denx.de/pipermail/u-boot/2014-September/188098.html

Patchwork [U-Boot,v3,1/3] mtd, spi: add MTD layer driver
http://patchwork.ozlabs.org/patch/386102/

Patchwork [U-Boot,v3,2/3] mtd, nand: move common functions from cmd_nand.c to common place
http://patchwork.ozlabs.org/patch/386103/

Patchwork [U-Boot,v3,3/3] spi, sf: use offset and size in sf cmd from mtdpartition
http://patchwork.ozlabs.org/patch/386101/

Quoted 94 lines

Quoted 87 lines

README +0 ~~-11~~

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
                 memories can be connected with a given cs line.
                 currently Xilinx Zynq qspi support these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
  - SystemACE Support:
                 CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
  #define STATUS_QEB_MXIC                (1 << 6)
  #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
  /* Flash timeout values */
  #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
  #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-31~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
  }
  #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
  /**
   * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
   *

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
                 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
         }
  #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");
 
         /* Release spi bus */
         spi_release_bus(spi);
--

Quoted 2 lines

1.9.1

Ping!

thanks!

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Jagan Teki

author

2014-12-23 08:15 UTC #3 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Hi Heiko,

Quoted 21 lines · Heiko Schocher

Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 9 lines
Quoted 6 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
  README                        | 11 -----------
  drivers/mtd/spi/sf_internal.h |  4 ----
  drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
  3 files changed, 45 deletions(-)

Quoted 2 lines

I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.

Did you test the same board on Linux? what about the status there?

Quoted 9 lines

BTW: What is with the patchset:
[U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands
http://lists.denx.de/pipermail/u-boot/2014-September/188098.html
Patchwork [U-Boot,v3,1/3] mtd, spi: add MTD layer driver
http://patchwork.ozlabs.org/patch/386102/

Quoted 7 lines

Patchwork [U-Boot,v3,2/3] mtd, nand: move common functions from cmd_nand.c to common place
http://patchwork.ozlabs.org/patch/386103/
Patchwork [U-Boot,v3,3/3] spi, sf: use offset and size in sf cmd from mtdpartition
http://patchwork.ozlabs.org/patch/386101/

Will come back next.

Quoted 95 lines

README +0 -0

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
                 memories can be connected with a given cs line.
                 currently Xilinx Zynq qspi support these type of

connections.

README +0 -4

-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined

with
- the W#/VPP signal provides hardware data protection for
the
- device as follows: When the enable/disable bit is set to
1,

README +0 -2

-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS

README +0 -3

-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
  - SystemACE Support:
                 CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
  #define STATUS_QEB_MXIC                (1 << 6)
  #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
  /* Flash timeout values */
  #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
  #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-28~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct
 spi_flash *flash)
  }
  #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
  /**
   * spi_flash_probe_slave() - Probe for a SPI flash device on a bus

drivers/mtd/spi/sf_probe.c +0 -2

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi,
 struct spi_flash *flash)
                 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
         }
  #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");

Quoted 7 lines

Quoted 7 lines
Quoted 5 lines
drivers/mtd/spi/sf_probe.c +0 -0
         /* Release spi bus */
         spi_release_bus(spi);
--
1.9.1
Ping!

thanks!

Signature · 1 line

Jagan.

Jagan Teki

author

2015-04-22 11:03 UTC #4 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Quoted 42 lines · Jagan Teki

Hi Heiko,
Quoted 21 lines · Heiko Schocher
Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 9 lines
Quoted 6 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
  README                        | 11 -----------
  drivers/mtd/spi/sf_internal.h |  4 ----
  drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
  3 files changed, 45 deletions(-)
Quoted 2 lines
I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.
Did you test the same board on Linux? what about the status there?
Quoted 13 lines
BTW: What is with the patchset:
[U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands
http://lists.denx.de/pipermail/u-boot/2014-September/188098.html
Patchwork [U-Boot,v3,1/3] mtd, spi: add MTD layer driver
http://patchwork.ozlabs.org/patch/386102/
Patchwork [U-Boot,v3,2/3] mtd, nand: move common functions from cmd_nand.c to common place
http://patchwork.ozlabs.org/patch/386103/

Quoted 108 lines

Quoted 3 lines

Patchwork [U-Boot,v3,3/3] spi, sf: use offset and size in sf cmd from mtdpartition
http://patchwork.ozlabs.org/patch/386101/

Will come back next.

Quoted 102 lines

Quoted 97 lines

README +0 -0

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
                 memories can be connected with a given cs line.
                 currently Xilinx Zynq qspi support these type of

connections.

README +0 -4

-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined

with
- the W#/VPP signal provides hardware data protection for
the
- device as follows: When the enable/disable bit is set to
1,

README +0 -2

-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS

README +0 -3

-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
  - SystemACE Support:
                 CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
  #define STATUS_QEB_MXIC                (1 << 6)
  #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
  /* Flash timeout values */
  #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
  #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-28~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct
 spi_flash *flash)
  }
  #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
  /**
   * spi_flash_probe_slave() - Probe for a SPI flash device on a bus

drivers/mtd/spi/sf_probe.c +0 -2

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi,
 struct spi_flash *flash)
                 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
         }
  #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");
 
         /* Release spi bus */

         spi_release_bus(spi);

Quoted 3 lines

--
1.9.1

Ping!

Signature · 1 line

Jagan.

Heiko Schocher

2015-04-23 05:39 UTC #5 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Hello Jagan,

Am 22.04.2015 13:03, schrieb Jagan Teki:

Quoted 152 lines · Jagan Teki

Quoted 42 lines

Hi Heiko,
Quoted 21 lines · Heiko Schocher
Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 9 lines
Quoted 6 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
   README                        | 11 -----------
   drivers/mtd/spi/sf_internal.h |  4 ----
   drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
   3 files changed, 45 deletions(-)
Quoted 2 lines
I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.
Did you test the same board on Linux? what about the status there?
Quoted 13 lines
BTW: What is with the patchset:
[U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands
http://lists.denx.de/pipermail/u-boot/2014-September/188098.html
Patchwork [U-Boot,v3,1/3] mtd, spi: add MTD layer driver
http://patchwork.ozlabs.org/patch/386102/
Patchwork [U-Boot,v3,2/3] mtd, nand: move common functions from cmd_nand.c to common place
http://patchwork.ozlabs.org/patch/386103/

Quoted 108 lines

Quoted 3 lines

Patchwork [U-Boot,v3,3/3] spi, sf: use offset and size in sf cmd from mtdpartition
http://patchwork.ozlabs.org/patch/386101/

Will come back next.

Quoted 102 lines

Quoted 97 lines

README +0 -0

index 4ca04d0..908646f 100644
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
                  memories can be connected with a given cs line.
                  currently Xilinx Zynq qspi support these type of

connections.

README +0 -4

-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined

with
- the W#/VPP signal provides hardware data protection for
the
- device as follows: When the enable/disable bit is set to
1,

README +0 -2

-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS

README +0 -3

-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
   - SystemACE Support:
                  CONFIG_SYSTEMACE

drivers/mtd/spi/sf_internal.h +0 -4

index 785f7a9..bd834dc 100644
@@ -97,10 +97,6 @@ enum {
   #define STATUS_QEB_MXIC                (1 << 6)
   #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
   /* Flash timeout values */
   #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
   #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

drivers/mtd/spi/sf_probe.c +0 ~~-28~~

index ce9987f..3b0e652 100644
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct
 spi_flash *flash)
   }
   #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
   /**
    * spi_flash_probe_slave() - Probe for a SPI flash device on a bus

drivers/mtd/spi/sf_probe.c +0 -2

@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi,
 struct spi_flash *flash)
                  puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
          }
   #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");
 
          /* Release spi bus */

          spi_release_bus(spi);

Quoted 3 lines

--
1.9.1

Ping!

Quoted 1 line

Ping!

I try to test it today.

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

2015-04-23 12:58 UTC #6 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

In reply to Jagan Teki

Hello Jagan,

Am 22.04.2015 13:03, schrieb Jagan Teki:

Quoted 25 lines · Jagan Teki

Quoted 24 lines
Hi Heiko,
Quoted 21 lines · Heiko Schocher
Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 16 lines
Quoted 13 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
   README                        | 11 -----------
   drivers/mtd/spi/sf_internal.h |  4 ----
   drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
   3 files changed, 45 deletions(-)

Quoted 4 lines

Quoted 4 lines
Quoted 2 lines
I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.
Did you test the same board on Linux? what about the status there?

You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it.

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Jagan Teki

author

2015-04-23 13:06 UTC #7 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Quoted 38 lines · Heiko Schocher

Hello Jagan,
Am 22.04.2015 13:03, schrieb Jagan Teki:
Quoted 35 lines · Jagan Teki
Quoted 33 lines
Hi Heiko,
Quoted 27 lines · Heiko Schocher
Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 11 lines
Quoted 7 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
   README                        | 11 -----------
   drivers/mtd/spi/sf_internal.h |  4 ----
   drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
   3 files changed, 45 deletions(-)
I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.

Quoted 5 lines

Quoted 1 line
Quoted 1 line
Did you test the same board on Linux? what about the status there?
You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it.

Ok, Shall I apply this revert patch?

thanks!

Signature · 1 line

Jagan.

Heiko Schocher

2015-04-23 13:09 UTC #8 lore raw

PATCH 1/1 Revert "spi: add config option to enable the WP pin function on st micron flashes"

Hello Jagan,

Am 23.04.2015 15:06, schrieb Jagan Teki:

Quoted 39 lines · Heiko Schocher

Quoted 38 lines
Hello Jagan,
Am 22.04.2015 13:03, schrieb Jagan Teki:
Quoted 35 lines · Jagan Teki
Quoted 33 lines
Hi Heiko,
Quoted 27 lines · Heiko Schocher
Hello Jagan,
Am 22.12.2014 09:58, schrieb Jagan Teki:
Quoted 11 lines
Quoted 7 lines · Jagannadha Sutradharudu Teki
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>
Cc Heiko Schocher <[email protected]>
---
    README                        | 11 -----------
    drivers/mtd/spi/sf_internal.h |  4 ----
    drivers/mtd/spi/sf_probe.c    | 30 ------------------------------
    3 files changed, 45 deletions(-)
I found this issue on the aristainetos board, there the "W#/Vpp" signal is connected to a gpio pin.

Quoted 7 lines

Quoted 5 lines
Quoted 1 line
Quoted 1 line
Did you test the same board on Linux? what about the status there?
You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it.
Ok, Shall I apply this revert patch?

Yes, please.

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany