i2c: scx200_acb: avoid I2C bus overclocking.
Subsystems (2)
PATCH 1/1 i2c: scx200_acb: avoid I2C bus overclocking.
According to I2C spec, max SCL rate is 100 kHz, but SCx200/CS5536 controller is currently driving it at 214 kHz according to my math.
SCL is derived from an input clock of 48 MHz, which must be divided by 480 (240 cycles for each SCL high/low state) to be within spec.
--- drivers/i2c/busses/scx200_acb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)
drivers/i2c/busses/scx200_acb.c +8 -7
@@ -46,6 +46,7 @@ module_param_array(base, int, NULL, 0);MODULE_PARM_DESC (base,"Base addresses for the ACCESS.bus controllers" );#define POLL_TIMEOUT (HZ/5) +#define ACBCLK 240/* 48 MHz / 100 kHz / 2 */ enum scx200_acb_state { state_idle,
@@ -255,14 +256,14 @@ static void scx200_acb_poll(struct scx200_acb_iface *iface)static void scx200_acb_reset (struct scx200_acb_iface *iface) {/* Disable the ACCESS.bus device and Configure the SCL -frequency: 16 clock cycles */ -outb (0x70 ,ACBCTL2 ); +frequency: 240 clock cycles => 100 kHz */ +outb (ACBCLK ,ACBCTL2 );/* Polling mode */ outb (0 ,ACBCTL1 );/* Disable slave address */ outb (0 ,ACBADDR );/* Enable the ACCESS.bus device */ -outb (inb (ACBCTL2 ) |ACBCTL2_ENABLE ,ACBCTL2 ); +outb (ACBCLK |ACBCTL2_ENABLE ,ACBCTL2 );/* Free STALL after START */ outb (inb (ACBCTL1 ) & ~(ACBCTL1_STASTRE |ACBCTL1_NMINTE ),ACBCTL1 );/* Send a STOP */
@@ -390,10 +391,10 @@ static int scx200_acb_probe(struct scx200_acb_iface *iface)u8 val;/* Disable the ACCESS.bus device and Configure the SCL -frequency: 16 clock cycles */ -outb (0x70 ,ACBCTL2 ); +frequency: 240 clock cycles => 100 kHz*/ +outb (ACBCLK ,ACBCTL2 ); -if (inb (ACBCTL2 ) !=0x70 ) { +if (inb (ACBCTL2 ) !=ACBCLK ) {pr_debug ("ACBCTL2 readback failed\n" );return -ENXIO ; }
@@ -406,7 +407,7 @@ static int scx200_acb_probe(struct scx200_acb_iface *iface)return -ENXIO ; } -outb (inb (ACBCTL2 ) |ACBCTL2_ENABLE ,ACBCTL2 ); +outb (ACBCLK |ACBCTL2_ENABLE ,ACBCTL2 );outb (inb (ACBCTL1 ) |ACBCTL1_NMINTE ,ACBCTL1 );
Signature · 1 line
2.4.0.rc1
A message that is not in the archive (sent off-list or not yet received): [email protected]
Quoted 7 lines · Svenning Sørensen
According to I2C spec, max SCL rate is 100 kHz, but SCx200/CS5536 controller is currently driving it at 214 kHz according to my math.
SCL is derived from an input clock of 48 MHz, which must be divided by 480 (240 cycles for each SCL high/low state) to be within spec.
Signed-off-by Svenning Soerensen <[email protected]>
So, did you test/measure the actual frequency? Or is this patch based on specs only? Thanks for caring about this old driver, though!
A message that is not in the archive (sent off-list or not yet received): 20150512201919.GL4449-oo5tB6JMkjKRinMKxDlMNPwbnWRJjS81@public.gmane.org
Quoted 4 lines · Wolfram Sang
Quoted 3 lines · Svenning Sørensen
According to I2C spec, max SCL rate is 100 kHz, but SCx200/CS5536 controller is currently driving it at 214 kHz according to my math.
Quoted 8 lines
Quoted 4 lines
SCL is derived from an input clock of 48 MHz, which must be divided by 480 (240 cycles for each SCL high/low state) to be within spec.
Signed-off-by Svenning Soerensen <[email protected]>So, did you test/measure the actual frequency? Or is this patch based on specs only? Thanks for caring about this old driver, though!
Unfortunately I don't have any scope, so it is based on datasheet only.
I noticed sporadic i2c errors reading the temperature on some of my PC Engines Alix.2 boards (with LM86 sensor chip) so started digging the datasheets and driver for an explanation.
I haven't noticed any problems after this change.
Quoted 7 lines · Svenning Sørensen
According to I2C spec, max SCL rate is 100 kHz, but SCx200/CS5536 controller is currently driving it at 214 kHz according to my math.
SCL is derived from an input clock of 48 MHz, which must be divided by 480 (240 cycles for each SCL high/low state) to be within spec.
Signed-off-by Svenning Soerensen <[email protected]>
Thanks for mentioning that it fixed a problem for you. I needed this info.
Quoted 1 line
+#define ACBCLK 240 /* 48 MHz / 100 kHz / 2 */
Can you add a comment where you found the info about 48MHz? Since I don't know the hardware at all: Can you imagine that there is even older hardware with a clock where 0x70 was suitable?
Quoted 2 lines
(quoted diff) +1
-1- outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); + outb(ACBCLK | ACBCTL2_ENABLE, ACBCTL2);
...
Review
Quoted 2 lines
(quoted diff) +1
-1- outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); + outb(ACBCLK | ACBCTL2_ENABLE, ACBCTL2);
For consistency reasons and to be less intrusive, I'd rather keep the original chunks.
Quoted 18 lines · Wolfram Sang
Quoted 7 lines · Svenning Sørensen
According to I2C spec, max SCL rate is 100 kHz, but SCx200/CS5536 controller is currently driving it at 214 kHz according to my math.
SCL is derived from an input clock of 48 MHz, which must be divided by 480 (240 cycles for each SCL high/low state) to be within spec.
Signed-off-by Svenning Soerensen <[email protected]>Thanks for mentioning that it fixed a problem for you. I needed this info.
Quoted 1 line
+#define ACBCLK 240 /* 48 MHz / 100 kHz / 2 */
Can you add a comment where you found the info about 48MHz? Since I don't know the hardware at all: Can you imagine that there is even older hardware with a clock where
0x70was suitable?
Quoted 8 lines
Quoted 2 lines
(quoted diff) +1
-1- outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); + outb(ACBCLK | ACBCTL2_ENABLE, ACBCTL2);...
Review
Quoted 2 lines
(quoted diff) +1
-1- outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); + outb(ACBCLK | ACBCTL2_ENABLE, ACBCTL2);For consistency reasons and to be less intrusive, I'd rather keep the original chunks.
I just remembered that this driver still has a maintainer :) Adding Jim to CC. Maybe he has some more info? Would be sad to lose this potential fix, yet I am careful to not introduce regressions to this old hardware.
Jim: The rest of this small thread can be found here:
http://patchwork.ozlabs.org/patch/464046/
Thanks,
Wolfram