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arm/ls102xa:Add support of conditional workaround implementation as per SoC ver

PATCH New Alison Wang 2 participants 2 messages Mar 12, 2015 – Apr 23, 2015 Arm (32-bit)

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Alison Wang

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PATCH v2 1/2 arm/ls102xa:Add support of conditional workaround implementation as per SoC ver

For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards.

Signed-off-by Alison Wang <[email protected]>

---
Changes in v2:
- Modify the subject to describe accurately
- Change SOC_VER_1_0 and SOC_VER_2_0 to SOC_MAJOR_VER_1_0 and SOC_MAJOR_VER_2_0
- Define a function instead of the piece of code which used in multiple places

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  3 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 68 ++++++++++++++++-------
 board/freescale/ls1021atwr/ls1021atwr.c           | 27 +++++++--
 3 files changed, 72 insertions(+), 26 deletions(-)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +3 -0
index 3a64afc..a8122c1 100644
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021		0x11
 #define SOC_VER_LS1022		0x12
 
+#define SOC_MAJOR_VER_1_0	0x1
+#define SOC_MAJOR_VER_2_0	0x2
+
 #define CCSR_BRR_OFFSET		0xe4
 #define CCSR_SCRATCHRW1_OFFSET	0x200
board/freescale/ls1021aqds/ls1021aqds.c +48 -20

112 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c +21 -6
index fb8525f..a9c87f2 100644
@@ -122,6 +122,17 @@ int checkboard(void)
 	return 0;
 }
 
+unsigned int get_soc_major_rev(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	unsigned int svr, major;
+
+	svr = in_be32(&gur->svr);
+	major = SVR_MAJ(svr);
+
+	return major;
+}
+
 void ddrmc_init(void)
 {
 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;

@@ -264,6 +275,7 @@ int board_early_init_f(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);

@@ -289,12 +301,15 @@ int board_early_init_f(void)
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
-	/*
-	 * Set CCI-400 Slave interface S1, S2 Shareable Override Register
-	 * All transactions are treated as non-shareable
-	 */
-	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	major = get_soc_major_rev();
+	if (major == SOC_MAJOR_VER_1_0) {
+		/*
+		 * Set CCI-400 Slave interface S1, S2 Shareable Override
+		 * Register All transactions are treated as non-shareable
+		 */
+		out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	}
 
 	return 0;
 }
Signature · 1 line
2.1.0.27.g96db324
Applied
#1 lore raw

PATCH v2 1/2 arm/ls102xa:Add support of conditional workaround implementation as per SoC ver

Quoted 10 lines · Alison Wang

For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards.

Signed-off-by Alison Wang <[email protected]>

---
Changes in v2:
- Modify the subject to describe accurately
- Change SOC_VER_1_0 and SOC_VER_2_0 to SOC_MAJOR_VER_1_0 and SOC_MAJOR_VER_2_0
- Define a function instead of the piece of code which used in multiple places

Applied to fsl-qoriq master, awaiting upstream.

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