armv8: caches: Added routine to set non cacheable region

PATCH New Michal Simek 4 participants 6 messages Apr 29, 2015 – May 14, 2015 Arm (32-bit)

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Michal Simek

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2015-04-29 08:35 UTC #0 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off.

Signed-off-by Siva Durga Prasad Paladugu <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Fix patch subject (remove addional zzz from v1)
- Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore)

 arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
 arch/arm/include/asm/system.h | 28 ++++++++++++++++++----------
 2 files changed, 41 insertions(+), 10 deletions(-)

arch/arm/cpu/armv8/cache_v8.c +23 -0

index c5ec5297cd39..25a2136a3cdf 100644
@@ -139,6 +139,24 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	/* get the level2_table0 start address */
+	u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);
+	u64 upto, end;
+
+	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+	      MMU_SECTION_SHIFT;
+	start = start >> MMU_SECTION_SHIFT;
+	for (upto = start; upto < end; upto++) {
+		page_table[upto] &= ~PMD_ATTRINDX_MASK;
+		page_table[upto] |= PMD_ATTRINDX(option);
+	}
+
+	flush_dcache_range(page_table[start], page_table[end]);
+	__asm_invalidate_tlb_all();
+}
 #else	/* CONFIG_SYS_DCACHE_OFF */
 
 void invalidate_dcache_all(void)

@@ -170,6 +188,11 @@ int dcache_status(void)
 	return 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+}
+
 #endif	/* CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF

arch/arm/include/asm/system.h +18 ~~-10~~

index 2a5bed2e46b6..c88687860ec1 100644
@@ -15,9 +15,15 @@
 #define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
 
 #define PGTABLE_SIZE	(0x10000)
+/* 2M granularity */
+#define MMU_SECTION_SHIFT	21
 
 #ifndef __ASSEMBLY__
 
+enum dcache_option {
+	DCACHE_OFF = 0x3,
+};
+
 #define isb()				\
 	({asm volatile(			\
 	"isb" : : : "memory");		\

@@ -211,16 +217,6 @@ enum {
 };
 
 /**
- * Change the cache settings for a region.
- *
- * \param start		start address of memory region to change
- * \param size		size of memory region to change
- * \param option	dcache option to select
- */
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option);
-
-/**
  * Register an update to the page tables, and flush the TLB
  *
  * \param start		start address of update in page table

@@ -241,4 +237,16 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 
 #endif /* CONFIG_ARM64 */
 
+#ifndef __ASSEMBLY__
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start		start address of memory region to change
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option);
+#endif /* __ASSEMBLY__ */
+
 #endif

Signature · 1 line

2.3.5

York Sun

2015-04-29 15:04 UTC #1 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

Quoted 25 lines · Michal Simek

Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off.
Signed-off-by Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
Changes in v2:
- Fix patch subject (remove addional zzz from v1)
- Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore)
 arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
 arch/arm/include/asm/system.h | 28 ++++++++++++++++++----------
 2 files changed, 41 insertions(+), 10 deletions(-)
arch/arm/cpu/armv8/cache_v8.c +0 -0
index c5ec5297cd39..25a2136a3cdf 100644

arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 146

Quoted 8 lines

arch/arm/cpu/armv8/cache_v8.c +5 -0

@@ -139,6 +139,24 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	/* get the level2_table0 start address */
+	u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);

How is this table address defined? For our SoC (fsl-lsch3), we have multiple level 2 tables. Using fixed address doesn't seem right here.

York

Mark Rutland

2015-04-29 16:29 UTC #2 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

In reply to Michal Simek

Hi Michal,

Quoted 2 lines · Michal Simek

Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.

What's the intended use of this?

Quoted 22 lines

Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off.
Signed-off-by Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
Changes in v2:
- Fix patch subject (remove addional zzz from v1)
- Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore)
 arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
 arch/arm/include/asm/system.h | 28 ++++++++++++++++++----------
 2 files changed, 41 insertions(+), 10 deletions(-)
arch/arm/cpu/armv8/cache_v8.c +0 -0
index c5ec5297cd39..25a2136a3cdf 100644

arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 146

Quoted 8 lines

arch/arm/cpu/armv8/cache_v8.c +5 -0

@@ -139,6 +139,24 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	/* get the level2_table0 start address */
+	u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);

This looks very specific to a particular platform.

arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 157

Quoted 11 lines

arch/arm/cpu/armv8/cache_v8.c +11 -0

+	u64 upto, end;
+
+	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+	      MMU_SECTION_SHIFT;
+	start = start >> MMU_SECTION_SHIFT;
+	for (upto = start; upto < end; upto++) {
+		page_table[upto] &= ~PMD_ATTRINDX_MASK;
+		page_table[upto] |= PMD_ATTRINDX(option);
+	}
+
+	flush_dcache_range(page_table[start], page_table[end]);

This looks odd. Aren't these the values in the page tables (complete with attributes), rather than (virtual) addresses?

What exactly are you trying to flush here? Depending on your TCR settings you don't necessarily have to flush the tables themselves, assuming they don't fall inside the region being changed?

arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 158

Quoted 1 line

arch/arm/cpu/armv8/cache_v8.c +1 -0
+	__asm_invalidate_tlb_all();

If the region was previously cacheable, you'll need to (clean+)invalidate here to clear the PA range in the caches.

Thanks,
Mark.

Siva Durga Prasad Paladugu

2015-05-12 03:46 UTC #3 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

Hi Mark,

Quoted 9 lines

-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, April 29, 2015 10:00 PM
To: Michal Simek
Cc: u-boot at lists.denx.de; Albert Aribaud; Marek Vasut; Tom Rini; Siva Durga Prasad Paladugu; Varun Sethi; Thierry Reding; Arnab Basu; York Sun
Subject: Re: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region

Quoted 7 lines

Hi Michal,
Quoted 2 lines · Michal Simek
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.
What's the intended use of this?

This is intended to mark a dynamically allocated region as non-cacheable region in runtime.
There is same kind of routine for armv7 but not for armv8. Do you think that the same functionality to be addressed for armv8 too?

As per below comment, you are correct, this looks like to be more board specific. We may have to move it to some board specific code.

Regards,
Siva

Quoted 62 lines

Quoted 2 lines
Define dummy routine for mmu_set_region_dcache_behaviour() to
handle
Quoted 22 lines
incase of dcache off.
Signed-off-by Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
Changes in v2:
- Fix patch subject (remove addional zzz from v1)
- Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore)
 arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
arch/arm/include/asm/system.h | 28 ++++++++++++++++++----------
 2 files changed, 41 insertions(+), 10 deletions(-)
(quoted diff) +0 -0
b/arch/arm/cpu/armv8/cache_v8.c index c5ec5297cd39..25a2136a3cdf 100644
arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 146
Quoted 8 lines
arch/arm/cpu/armv8/cache_v8.c +5 -0
@@ -139,6 +139,24 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	/* get the level2_table0 start address */
+	u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);
This looks very specific to a particular platform.
arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 157
Quoted 11 lines
arch/arm/cpu/armv8/cache_v8.c +11 -0
+	u64 upto, end;
+
+	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+	      MMU_SECTION_SHIFT;
+	start = start >> MMU_SECTION_SHIFT;
+	for (upto = start; upto < end; upto++) {
+		page_table[upto] &= ~PMD_ATTRINDX_MASK;
+		page_table[upto] |= PMD_ATTRINDX(option);
+	}
+
+	flush_dcache_range(page_table[start], page_table[end]);
This looks odd. Aren't these the values in the page tables (complete with attributes), rather than (virtual) addresses?
What exactly are you trying to flush here? Depending on your TCR settings you don't necessarily have to flush the tables themselves, assuming they don't fall inside the region being changed?
arch/arm/cpu/armv8/cache_v8.c int dcache_status(void) · line 158
Quoted 1 line
arch/arm/cpu/armv8/cache_v8.c +1 -0
+	__asm_invalidate_tlb_all();
If the region was previously cacheable, you'll need to (clean+)invalidate here to clear the PA range in the caches.
Thanks,
Mark.

Mark Rutland

2015-05-13 17:31 UTC #4 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

Quoted 12 lines · Siva Durga Prasad Paladugu

Hi Mark,
Quoted 9 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, April 29, 2015 10:00 PM
To: Michal Simek
Cc: u-boot at lists.denx.de; Albert Aribaud; Marek Vasut; Tom Rini; Siva Durga Prasad Paladugu; Varun Sethi; Thierry Reding; Arnab Basu; York Sun
Subject: Re: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region

Quoted 8 lines

Quoted 7 lines
Hi Michal,
Quoted 2 lines · Michal Simek
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.
What's the intended use of this?
This is intended to mark a dynamically allocated region as non-cacheable region in runtime.

Sure, but why does that region need to be non-cacheable?

I assume you want to give the region to some device?

Do you ever hand the memory back (and hence need to make it cacehable again)?

Quoted 3 lines

There is same kind of routine for armv7 but not for armv8. Do you think that the same functionality to be addressed for armv8 too?
As per below comment, you are correct, this looks like to be more board specific.

While the address of the tables might be board-specific I'd imagine that the manipulation routines can be shared.

Thanks,
Mark.

Siva Durga Prasad Paladugu

2015-05-14 05:01 UTC #5 lore raw

PATCH v2 1/1 armv8: caches: Added routine to set non cacheable region

Hi Mark,

Quoted 30 lines

-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, May 13, 2015 11:01 PM
To: Siva Durga Prasad Paladugu
Cc: Michal Simek; u-boot at lists.denx.de; Albert Aribaud; Marek Vasut; Tom Rini; Varun Sethi; Thierry Reding; Arnab Basu; York Sun
Subject: Re: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region
Quoted 19 lines · Siva Durga Prasad Paladugu
Hi Mark,
Quoted 16 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, April 29, 2015 10:00 PM
To: Michal Simek
Cc: u-boot at lists.denx.de; Albert Aribaud; Marek Vasut; Tom Rini; Siva Durga Prasad Paladugu; Varun Sethi; Thierry Reding; Arnab Basu; York Sun
Subject: Re: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region
Hi Michal,
Quoted 2 lines · Michal Simek
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable.

Quoted 7 lines

Quoted 2 lines
Quoted 1 line
What's the intended use of this?
This is intended to mark a dynamically allocated region as non-cacheable
region in runtime.
Sure, but why does that region need to be non-cacheable?
I assume you want to give the region to some device?

Yes, this is used for device.

Quoted 3 lines

Do you ever hand the memory back (and hence need to make it cacehable again)?

No, In my case , I don't need to make it cacheable back...

Quoted 9 lines

Quoted 2 lines
There is same kind of routine for armv7 but not for armv8. Do you think
that the same functionality to be addressed for armv8 too?
Quoted 2 lines
As per below comment, you are correct, this looks like to be more board
specific.
While the address of the tables might be board-specific I'd imagine that the manipulation routines can be shared.

Ok, I got it, I will check how to make these manipulation routines generic and will send v2.

Thanks,
Siva

Quoted 3 lines

Thanks,
Mark.