powerpc/t4rdb: Add SD boot support for T4240RDB board

PATCH New Chunhe Lan 2 participants 2 messages Mar 20, 2015 – May 5, 2015 PowerPC

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Chunhe Lan

author

2015-03-20 09:08 UTC #0 lore raw

PATCH 1/1 powerpc/t4rdb: Add SD boot support for T4240RDB board

This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot.

Signed-off-by Chunhe Lan <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/Kconfig  |    1 +
 board/freescale/t4rdb/MAINTAINERS |    1 +
 board/freescale/t4rdb/Makefile    |    6 ++-
 board/freescale/t4rdb/ddr.c       |    6 ++-
 board/freescale/t4rdb/spl.c       |   95 +++++++++++++++++++++++++++++++++++++
 board/freescale/t4rdb/t4_pbi.cfg  |    3 -
 board/freescale/t4rdb/t4_rcw.cfg  |    6 +-
 board/freescale/t4rdb/tlb.c       |    8 +++
 configs/T4240RDB_SDCARD_defconfig |    5 ++
 include/configs/T4240RDB.h        |   71 ++++++++++++++++++++++++---
 10 files changed, 186 insertions(+), 16 deletions(-)
 create mode 100644 board/freescale/t4rdb/spl.c
 create mode 100644 configs/T4240RDB_SDCARD_defconfig

arch/powerpc/cpu/mpc85xx/Kconfig +1 -0

index adb5bd3..27eea29 100644
@@ -131,6 +131,7 @@ config TARGET_T4240QDS
 
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
+	select SUPPORT_SPL
 
 config TARGET_CONTROLCENTERD
 	bool "Support controlcenterd"

board/freescale/t4rdb/MAINTAINERS +1 -0

index 845c1b6..53ccabc 100644
@@ -5,3 +5,4 @@ F:	board/freescale/t4rdb/
 F:	include/configs/T4240RDB.h
 F:	configs/T4160RDB_defconfig
 F:	configs/T4240RDB_defconfig
+F:	configs/T4240RDB_SDCARD_defconfig

board/freescale/t4rdb/Makefile +5 -1

index 3886e3d..83b55ee 100644
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240RDB) += t4240rdb.o
 obj-y	+= cpld.o
-obj-y	+= ddr.o
 obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
+endif
+obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o

board/freescale/t4rdb/ddr.c +5 -1

index 5a43c1b..27b37b5 100644
@@ -108,11 +108,15 @@ phys_size_t initdram(int board_type)
 
 	puts("Initializing....using SPD\n");
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
 
-	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/t4rdb/spl.c new file +95 -0

95 lines not on this page · raw message

board/freescale/t4rdb/t4_pbi.cfg +0 -3

index c9f8ced..e7bb673 100644
@@ -19,9 +19,6 @@
 09000d00 00000000
 09000d04 fff80000
 09000d08 81000012
-#slow mdio clock
-095fc030 00008148
-095fd030 00808148
 #Configure alternate space
 09000010 00000000
 09000014 ff000000

board/freescale/t4rdb/t4_rcw.cfg +3 -3

index e46c7b2..282fea4 100644
@@ -2,6 +2,6 @@
 aa55aa55 010e0100
 #serdes protocol  27_55_1_9
 16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000287fc
-00000000 50000000 00000000 00000028
+6c6e0848 00448c00 ec020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028

board/freescale/t4rdb/tlb.c +8 -0

index 474301e..6a6b4b5 100644
@@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
+
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 18, BOOKE_PAGESZ_2G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

configs/T4240RDB_SDCARD_defconfig new file +5 -0

new file mode 100644
index 0000000..648b789
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T4240RDB=y

include/configs/T4240RDB.h +63 -8

113 lines not on this page · raw message

Signature · 1 line

1.7.6.5

York Sun

2015-05-05 16:29 UTC #1 lore raw

PATCH 1/1 powerpc/t4rdb: Add SD boot support for T4240RDB board

Quoted 7 lines · Chunhe Lan

This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot.
Signed-off-by Chunhe Lan <[email protected]>

Quoted 11 lines

---
 arch/powerpc/cpu/mpc85xx/Kconfig  |    1 +
 board/freescale/t4rdb/MAINTAINERS |    1 +
 board/freescale/t4rdb/Makefile    |    6 ++-
 board/freescale/t4rdb/ddr.c       |    6 ++-
 board/freescale/t4rdb/spl.c       |   95 +++++++++++++++++++++++++++++++++++++
 board/freescale/t4rdb/t4_pbi.cfg  |    3 -
 board/freescale/t4rdb/t4_rcw.cfg  |    6 +-
 board/freescale/t4rdb/tlb.c       |    8 +++
 configs/T4240RDB_SDCARD_defconfig |    5 ++
 include/configs/T4240RDB.h        |   71 ++++++++++++++++++++++++---

Fixed defconfig file. Applied to u-boot-mpc85xx master. Awaiting upstream.

York