Add flexcan support for LS1021A SoCs

This patch adds ls1021a flexcan device entry to the flexcan driver code.

Signed-off-by Bhupesh Sharma <[email protected]>

---
 drivers/net/can/flexcan.c |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

drivers/net/can/flexcan.c +1 -0

index ad0a7e8..deaa24e 100644
@@ -267,10 +267,26 @@ static struct flexcan_devtype_data fsl_imx28_devtype_data;
 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 	.features = FLEXCAN_HAS_V10_FEATURES,
 };
+

drivers/net/can/flexcan.c +75 -74

  static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
  {

@@ -356,14 +366,14 @@ static int flexcan_chip_enable(struct flexcan_priv *priv)
      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg &= ~FLEXCAN_MCR_MDIS;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+     while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
              return -ETIMEDOUT;
 
      return 0;

@@ -375,14 +385,14 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_MDIS;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+     while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
              udelay(10);
 
-     if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+     if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
              return -ETIMEDOUT;
 
      return 0;

@@ -394,14 +404,14 @@ static int flexcan_chip_freeze(struct flexcan_priv *priv)
      unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_HALT;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+     while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
              udelay(100);
 
-     if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+     if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
              return -ETIMEDOUT;
 
      return 0;

@@ -413,14 +423,14 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg &= ~FLEXCAN_MCR_HALT;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+     while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
              return -ETIMEDOUT;
 
      return 0;

@@ -431,23 +441,22 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
      struct flexcan_regs __iomem *regs = priv->base;
      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 
-     flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
-     while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+     priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+     while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
              return -ETIMEDOUT;
 
      return 0;
  }
 
-
  static int __flexcan_get_berr_counter(const struct net_device *dev,
                                    struct can_berr_counter *bec)
  {
      const struct flexcan_priv *priv = netdev_priv(dev);
      struct flexcan_regs __iomem *regs = priv->base;
-     u32 reg = flexcan_read(&regs->ecr);
+     u32 reg = priv->read(&regs->ecr);
 
      bec->txerr = (reg >> 0) & 0xff;
      bec->rxerr = (reg >> 8) & 0xff;

@@ -503,24 +512,24 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
      if (cf->can_dlc > 0) {
              u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
-             flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
+             priv->write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
      }
      if (cf->can_dlc > 3) {
              u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
-             flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
+             priv->write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
      }
 
      can_put_echo_skb(skb, dev, 0);
 
-     flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
-     flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+     priv->write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+     priv->write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
      /* Errata ERR005829 step8:
       * Write twice INACTIVE(0x8) code to first MB.
       */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
      return NETDEV_TX_OK;

@@ -645,8 +654,8 @@ static void flexcan_read_fifo(const struct net_device *dev,
      struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
      u32 reg_ctrl, reg_id;
 
-     reg_ctrl = flexcan_read(&mb->can_ctrl);
-     reg_id = flexcan_read(&mb->can_id);
+     reg_ctrl = priv->read(&mb->can_ctrl);
+     reg_id = priv->read(&mb->can_id);
      if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
              cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
      else

@@ -656,12 +665,12 @@ static void flexcan_read_fifo(const struct net_device *dev,
              cf->can_id |= CAN_RTR_FLAG;
      cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 
-     *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
-     *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
+     *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+     *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 
      /* mark as read */
-     flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
-     flexcan_read(&regs->timer);
+     priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+     priv->read(&regs->timer);
  }
 
  static int flexcan_read_frame(struct net_device *dev)

@@ -699,17 +708,17 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
       * The error bits are cleared on read,
       * use saved value from irq handler.
       */
-     reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
+     reg_esr = priv->read(&regs->esr) | priv->reg_esr;
 
      /* handle state changes */
      work_done += flexcan_poll_state(dev, reg_esr);
 
      /* handle RX-FIFO */
-     reg_iflag1 = flexcan_read(&regs->iflag1);
+     reg_iflag1 = priv->read(&regs->iflag1);
      while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
             work_done < quota) {
              work_done += flexcan_read_frame(dev);
-             reg_iflag1 = flexcan_read(&regs->iflag1);
+             reg_iflag1 = priv->read(&regs->iflag1);
      }
 
      /* report bus errors */

@@ -719,8 +728,8 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
      if (work_done < quota) {
              napi_complete(napi);
              /* enable IRQs */
-             flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
-             flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+             priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+             priv->write(priv->reg_ctrl_default, &regs->ctrl);
      }
 
      return work_done;

@@ -734,11 +743,11 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
      struct flexcan_regs __iomem *regs = priv->base;
      u32 reg_iflag1, reg_esr;
 
-     reg_iflag1 = flexcan_read(&regs->iflag1);
-     reg_esr = flexcan_read(&regs->esr);
+     reg_iflag1 = priv->read(&regs->iflag1);
+     reg_esr = priv->read(&regs->esr);
      /* ACK all bus error and state change IRQ sources */
      if (reg_esr & FLEXCAN_ESR_ALL_INT)
-             flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+             priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 
      /*
       * schedule NAPI in case of:

@@ -754,16 +763,16 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
               * save them for later use.
               */
              priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
-             flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+             priv->write(FLEXCAN_IFLAG_DEFAULT &
                      ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
-             flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+             priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
                     &regs->ctrl);
              napi_schedule(&priv->napi);
      }
 
      /* FIFO overflow */
      if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
-             flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+             priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
              dev->stats.rx_over_errors++;
              dev->stats.rx_errors++;
      }

@@ -774,9 +783,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
              stats->tx_packets++;
              can_led_event(dev, CAN_LED_EVENT_TX);
              /* after sending a RTR frame mailbox is in RX mode */
-             flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+             priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                            &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-             flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+             priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
              netif_wake_queue(dev);
      }
 

@@ -790,7 +799,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
      struct flexcan_regs __iomem *regs = priv->base;
      u32 reg;
 
-     reg = flexcan_read(&regs->ctrl);
+     reg = priv->read(&regs->ctrl);
      reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
               FLEXCAN_CTRL_RJW(0x3) |
               FLEXCAN_CTRL_PSEG1(0x7) |

@@ -814,11 +823,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
              reg |= FLEXCAN_CTRL_SMP;
 
      netdev_info(dev, "writing ctrl=0x%08x\n", reg);
-     flexcan_write(reg, &regs->ctrl);
+     priv->write(reg, &regs->ctrl);
 
      /* print chip status */
      netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
-                flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+                priv->read(&regs->mcr), priv->read(&regs->ctrl));
  }
 
  /*

@@ -858,14 +867,14 @@ static int flexcan_chip_start(struct net_device *dev)
       * disable local echo
       *
       */
-     reg_mcr = flexcan_read(&regs->mcr);
+     reg_mcr = priv->read(&regs->mcr);
      reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
      reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
              FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
              FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
              FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
      netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
-     flexcan_write(reg_mcr, &regs->mcr);
+     priv->write(reg_mcr, &regs->mcr);
 
      /*
       * CTRL

@@ -879,7 +888,7 @@ static int flexcan_chip_start(struct net_device *dev)
       * enable bus off interrupt
       * (== FLEXCAN_CTRL_ERR_STATE)
       */
-     reg_ctrl = flexcan_read(&regs->ctrl);
+     reg_ctrl = priv->read(&regs->ctrl);
      reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
      reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
              FLEXCAN_CTRL_ERR_STATE;

@@ -897,29 +906,29 @@ static int flexcan_chip_start(struct net_device *dev)
      /* save for later use */
      priv->reg_ctrl_default = reg_ctrl;
      netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
-     flexcan_write(reg_ctrl, &regs->ctrl);
+     priv->write(reg_ctrl, &regs->ctrl);
 
      /* clear and invalidate all mailboxes first */
      for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
-             flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
+             priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
                            &regs->cantxfg[i].can_ctrl);
      }
 
      /* Errata ERR005829: mark first TX mailbox as INACTIVE */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
      /* mark TX mailbox as INACTIVE */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
      /* acceptance mask/acceptance code (accept everything) */
-     flexcan_write(0x0, &regs->rxgmask);
-     flexcan_write(0x0, &regs->rx14mask);
-     flexcan_write(0x0, &regs->rx15mask);
+     priv->write(0x0, &regs->rxgmask);
+     priv->write(0x0, &regs->rx14mask);
+     priv->write(0x0, &regs->rx15mask);
 
      if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
-             flexcan_write(0x0, &regs->rxfgmask);
+             priv->write(0x0, &regs->rxfgmask);
 
      /*
       * On Vybrid, disable memory error detection interrupts

@@ -934,16 +943,16 @@ static int flexcan_chip_start(struct net_device *dev)
               * and Correction of Memory Errors" to write to
               * MECR register
               */
-             reg_crl2 = flexcan_read(&regs->crl2);
+             reg_crl2 = priv->read(&regs->crl2);
              reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
-             flexcan_write(reg_crl2, &regs->crl2);
+             priv->write(reg_crl2, &regs->crl2);
 
-             reg_mecr = flexcan_read(&regs->mecr);
+             reg_mecr = priv->read(&regs->mecr);
              reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
-             flexcan_write(reg_mecr, &regs->mecr);
+             priv->write(reg_mecr, &regs->mecr);
              reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
                              FLEXCAN_MECR_FANCEI_MSK);
-             flexcan_write(reg_mecr, &regs->mecr);
+             priv->write(reg_mecr, &regs->mecr);
      }
 
      err = flexcan_transceiver_enable(priv);

@@ -958,11 +967,11 @@ static int flexcan_chip_start(struct net_device *dev)
      priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
      /* enable FIFO interrupts */
-     flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+     priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 
      /* print chip status */
      netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
-                flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+                priv->read(&regs->mcr), priv->read(&regs->ctrl));
 
      return 0;
 

@@ -989,8 +998,8 @@ static void flexcan_chip_stop(struct net_device *dev)
      flexcan_chip_disable(priv);
 
      /* Disable all interrupts */
-     flexcan_write(0, &regs->imask1);
-     flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+     priv->write(0, &regs->imask1);
+     priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
                    &regs->ctrl);
 
      flexcan_transceiver_disable(priv);

@@ -1108,26 +1117,26 @@ static int register_flexcandev(struct net_device *dev)
      err = flexcan_chip_disable(priv);
      if (err)
              goto out_disable_per;
-     reg = flexcan_read(&regs->ctrl);
+     reg = priv->read(&regs->ctrl);
      reg |= FLEXCAN_CTRL_CLK_SRC;
-     flexcan_write(reg, &regs->ctrl);
+     priv->write(reg, &regs->ctrl);
 
      err = flexcan_chip_enable(priv);
      if (err)
              goto out_chip_disable;
 
      /* set freeze, halt and activate FIFO, restrict register access */
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
              FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
      /*
       * Currently we only support newer versions of this core
       * featuring a RX FIFO. Older cores found on some Coldfire
       * derivates are not yet supported.
       */
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      if (!(reg & FLEXCAN_MCR_FEN)) {
              netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
              err = -ENODEV;

@@ -1183,6 +1192,8 @@ static int flexcan_probe(struct platform_device *pdev)
      void __iomem *base;
      int err, irq;
      u32 clock_freq = 0;
+     /* Default case for most ARM based FSL SoC having BE FlexCAN IP */
+     bool core_is_little = true, module_is_little = false;
 
      reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
      if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)

-----Original Message-----
From: Enrico Weigelt, metux IT consult [mailto:weigelt at melag.de] Am 14.05.2015 um 13:33 schrieb Bhupesh Sharma:

drivers/net/can/flexcan.c struct flexcan_priv { · line 264

Quoted 12 lines

drivers/net/can/flexcan.c +4 -0

index deaa24e..b0222ae 100644
@@ -258,6 +258,10 @@ struct flexcan_priv {
      struct flexcan_platform_data *pdata;
      const struct flexcan_devtype_data *devtype_data;
      struct regulator *reg_xceiver;
+
+     /* Read and Write APIs */
+     u32 (*read)(void __iomem *addr);
+     void (*write)(u32 val, void __iomem *addr);

Does it *really* need to be a far call ?
Why not just give the existing flexcan_read()/flexcan_write() inline's an additional bit to decide whether to swab or not ?

drivers/net/can/flexcan.c static const struct can_bittiming_const flexcan_bittiming_const = { · line 320

Quoted 3 lines

drivers/net/can/flexcan.c +1 -2

-#if defined(CONFIG_PPC)
-static inline u32 flexcan_read(void __iomem *addr)
+static inline u32 flexcan_read_le(void __iomem *addr)

_static inline_ as a callback ? seriously ?

drivers/net/can/flexcan.c struct flexcan_priv { · line 266

Quoted 1 line

drivers/net/can/flexcan.c +0 -0

  static inline int flexcan_transceiver_enable(const struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_enable(struct

Quoted 2 lines

drivers/net/can/flexcan.c +0 -0

  {

@@ -356,14 +366,14 @@ static int flexcan_chip_enable(struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_enable(struct flexcan_priv *priv)

Quoted 10 lines

drivers/net/can/flexcan.c +2 -3

      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg &= ~FLEXCAN_MCR_MDIS;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && (flexcan_read(&regs->mcr) &

FLEXCAN_MCR_LPM_ACK))

drivers/net/can/flexcan.c static int flexcan_chip_disable(struct

Quoted 10 lines

drivers/net/can/flexcan.c +3 -1

+     while (timeout-- && (priv->read(&regs->mcr) &
+ FLEXCAN_MCR_LPM_ACK))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
              return -ETIMEDOUT;
 
      return 0;

@@ -375,14 +385,14 @@ static int flexcan_chip_disable(struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_disable(struct flexcan_priv *priv)

Quoted 10 lines

drivers/net/can/flexcan.c +2 -3

      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_MDIS;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && !(flexcan_read(&regs->mcr) &

FLEXCAN_MCR_LPM_ACK))

drivers/net/can/flexcan.c static int flexcan_chip_freeze(struct

Quoted 10 lines

drivers/net/can/flexcan.c +3 -1

+     while (timeout-- && !(priv->read(&regs->mcr) &
+ FLEXCAN_MCR_LPM_ACK))
              udelay(10);
 
-     if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+     if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
              return -ETIMEDOUT;
 
      return 0;

@@ -394,14 +404,14 @@ static int flexcan_chip_freeze(struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_freeze(struct flexcan_priv *priv)

Quoted 11 lines

drivers/net/can/flexcan.c +2 -3

      unsigned int timeout = 1000 * 1000 * 10 / priv-
 can.bittiming.bitrate;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_HALT;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && !(flexcan_read(&regs->mcr) &

FLEXCAN_MCR_FRZ_ACK))

drivers/net/can/flexcan.c static int flexcan_chip_unfreeze(struct

Quoted 10 lines

drivers/net/can/flexcan.c +3 -1

+     while (timeout-- && !(priv->read(&regs->mcr) &
+ FLEXCAN_MCR_FRZ_ACK))
              udelay(100);
 
-     if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+     if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
              return -ETIMEDOUT;
 
      return 0;

@@ -413,14 +423,14 @@ static int flexcan_chip_unfreeze(struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_unfreeze(struct flexcan_priv *priv)

Quoted 10 lines

drivers/net/can/flexcan.c +2 -3

      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
      u32 reg;
 
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg &= ~FLEXCAN_MCR_HALT;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);
 
-     while (timeout-- && (flexcan_read(&regs->mcr) &

FLEXCAN_MCR_FRZ_ACK))

drivers/net/can/flexcan.c static int flexcan_chip_softreset(struct

Quoted 10 lines

drivers/net/can/flexcan.c +3 -1

+     while (timeout-- && (priv->read(&regs->mcr) &
+ FLEXCAN_MCR_FRZ_ACK))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
              return -ETIMEDOUT;
 
      return 0;

@@ -431,23 +441,22 @@ static int flexcan_chip_softreset(struct

flexcan_priv *priv)

drivers/net/can/flexcan.c static int flexcan_chip_softreset(struct flexcan_priv *priv)

Quoted 5 lines

drivers/net/can/flexcan.c +0 -2

      struct flexcan_regs __iomem *regs = priv->base;
      unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 
-     flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
-     while (timeout-- && (flexcan_read(&regs->mcr) &

FLEXCAN_MCR_SOFTRST))

drivers/net/can/flexcan.c static void flexcan_read_fifo(const struct

Quoted 60 lines

drivers/net/can/flexcan.c +13 -9

+     priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+     while (timeout-- && (priv->read(&regs->mcr) &
+ FLEXCAN_MCR_SOFTRST))
              udelay(10);
 
-     if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+     if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
              return -ETIMEDOUT;
 
      return 0;
  }
 
-
  static int __flexcan_get_berr_counter(const struct net_device *dev,
                                    struct can_berr_counter *bec)
  {
      const struct flexcan_priv *priv = netdev_priv(dev);
      struct flexcan_regs __iomem *regs = priv->base;
-     u32 reg = flexcan_read(&regs->ecr);
+     u32 reg = priv->read(&regs->ecr);
 
      bec->txerr = (reg >> 0) & 0xff;
      bec->rxerr = (reg >> 8) & 0xff;

@@ -503,24 +512,24 @@ static int flexcan_start_xmit(struct sk_buff
 *skb, struct net_device *dev)
 
      if (cf->can_dlc > 0) {
              u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
-             flexcan_write(data, &regs-
 cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
+             priv->write(data,
+ &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
      }
      if (cf->can_dlc > 3) {
              u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
-             flexcan_write(data, &regs-
 cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
+             priv->write(data,
+ &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
      }
 
      can_put_echo_skb(skb, dev, 0);
 
-     flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
-     flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+     priv->write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+     priv->write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
      /* Errata ERR005829 step8:
       * Write twice INACTIVE(0x8) code to first MB.
       */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
      return NETDEV_TX_OK;

@@ -645,8 +654,8 @@ static void flexcan_read_fifo(const struct

net_device *dev,

drivers/net/can/flexcan.c static void flexcan_read_fifo(const struct net_device *dev,

Quoted 9 lines

drivers/net/can/flexcan.c +2 -2

      struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
      u32 reg_ctrl, reg_id;
 
-     reg_ctrl = flexcan_read(&mb->can_ctrl);
-     reg_id = flexcan_read(&mb->can_id);
+     reg_ctrl = priv->read(&mb->can_ctrl);
+     reg_id = priv->read(&mb->can_id);
      if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
              cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) |

CAN_EFF_FLAG;

drivers/net/can/flexcan.c static void flexcan_read_fifo(const struct

Quoted 2 lines

drivers/net/can/flexcan.c +0 -0

      else

@@ -656,12 +665,12 @@ static void flexcan_read_fifo(const struct

net_device *dev,

drivers/net/can/flexcan.c static int flexcan_poll(struct napi_struct *napi,

Quoted 42 lines

drivers/net/can/flexcan.c +9 -7

              cf->can_id |= CAN_RTR_FLAG;
      cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 
-     *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb-
 data[0]));
-     *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb-
 data[1]));
+     *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb-
 data[0]));
+     *(__be32 *)(cf->data + 4) =
+ cpu_to_be32(priv->read(&mb->data[1]));
 
      /* mark as read */
-     flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
-     flexcan_read(&regs->timer);
+     priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+     priv->read(&regs->timer);
  }
 
  static int flexcan_read_frame(struct net_device *dev) @@ -699,17
+708,17 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
       * The error bits are cleared on read,
       * use saved value from irq handler.
       */
-     reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
+     reg_esr = priv->read(&regs->esr) | priv->reg_esr;
 
      /* handle state changes */
      work_done += flexcan_poll_state(dev, reg_esr);
 
      /* handle RX-FIFO */
-     reg_iflag1 = flexcan_read(&regs->iflag1);
+     reg_iflag1 = priv->read(&regs->iflag1);
      while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
             work_done < quota) {
              work_done += flexcan_read_frame(dev);
-             reg_iflag1 = flexcan_read(&regs->iflag1);
+             reg_iflag1 = priv->read(&regs->iflag1);
      }
 
      /* report bus errors */

@@ -719,8 +728,8 @@ static int flexcan_poll(struct napi_struct *napi,

int quota)

drivers/net/can/flexcan.c static irqreturn_t flexcan_irq(int irq, void

Quoted 11 lines

drivers/net/can/flexcan.c +2 -2

      if (work_done < quota) {
              napi_complete(napi);
              /* enable IRQs */
-             flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
-             flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+             priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+             priv->write(priv->reg_ctrl_default, &regs->ctrl);
      }
 
      return work_done;

@@ -734,11 +743,11 @@ static irqreturn_t flexcan_irq(int irq, void

*dev_id)

drivers/net/can/flexcan.c static irqreturn_t flexcan_irq(int irq, void

Quoted 15 lines

drivers/net/can/flexcan.c +3 -3

      struct flexcan_regs __iomem *regs = priv->base;
      u32 reg_iflag1, reg_esr;
 
-     reg_iflag1 = flexcan_read(&regs->iflag1);
-     reg_esr = flexcan_read(&regs->esr);
+     reg_iflag1 = priv->read(&regs->iflag1);
+     reg_esr = priv->read(&regs->esr);
      /* ACK all bus error and state change IRQ sources */
      if (reg_esr & FLEXCAN_ESR_ALL_INT)
-             flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+             priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 
      /*
       * schedule NAPI in case of:

@@ -754,16 +763,16 @@ static irqreturn_t flexcan_irq(int irq, void

*dev_id)

drivers/net/can/flexcan.c static irqreturn_t flexcan_irq(int irq, void *dev_id)

Quoted 7 lines

drivers/net/can/flexcan.c +1 -2

               * save them for later use.
               */
              priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
-             flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+             priv->write(FLEXCAN_IFLAG_DEFAULT &
                      ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
-             flexcan_write(priv->reg_ctrl_default &

~FLEXCAN_CTRL_ERR_ALL,

drivers/net/can/flexcan.c static irqreturn_t flexcan_irq(int irq, void

Quoted 16 lines

drivers/net/can/flexcan.c +4 -1

+             priv->write(priv->reg_ctrl_default &
+ ~FLEXCAN_CTRL_ERR_ALL,
                     &regs->ctrl);
              napi_schedule(&priv->napi);
      }
 
      /* FIFO overflow */
      if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
-             flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs-
 iflag1);
+             priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
+ &regs->iflag1);
              dev->stats.rx_over_errors++;
              dev->stats.rx_errors++;
      }

@@ -774,9 +783,9 @@ static irqreturn_t flexcan_irq(int irq, void

*dev_id)

drivers/net/can/flexcan.c static void flexcan_set_bittiming(struct net_device

Quoted 13 lines

drivers/net/can/flexcan.c +2 -2

              stats->tx_packets++;
              can_led_event(dev, CAN_LED_EVENT_TX);
              /* after sending a RTR frame mailbox is in RX mode */
-             flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+             priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                            &regs-
 cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-             flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+             priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
              netif_wake_queue(dev);
      }

@@ -790,7 +799,7 @@ static void flexcan_set_bittiming(struct net_device

*dev)

drivers/net/can/flexcan.c static int flexcan_chip_start(struct net_device

Quoted 23 lines

drivers/net/can/flexcan.c +1 -1

      struct flexcan_regs __iomem *regs = priv->base;
      u32 reg;
 
-     reg = flexcan_read(&regs->ctrl);
+     reg = priv->read(&regs->ctrl);
      reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
               FLEXCAN_CTRL_RJW(0x3) |
               FLEXCAN_CTRL_PSEG1(0x7) | @@ -814,11 +823,11 @@ static

void flexcan_set_bittiming(struct net_device *dev)

              reg |= FLEXCAN_CTRL_SMP;

      netdev_info(dev, "writing ctrl=0x%08x\n", reg);

drivers/net/can/flexcan.c +2 -2

-     flexcan_write(reg, &regs->ctrl);
+     priv->write(reg, &regs->ctrl);
 
      /* print chip status */
      netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
-                flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+                priv->read(&regs->mcr), priv->read(&regs->ctrl));
  }
 
  /*

@@ -858,14 +867,14 @@ static int flexcan_chip_start(struct net_device

*dev)

drivers/net/can/flexcan.c static int flexcan_chip_start(struct net_device

Quoted 17 lines

drivers/net/can/flexcan.c +2 -2

       * disable local echo
       *
       */
-     reg_mcr = flexcan_read(&regs->mcr);
+     reg_mcr = priv->read(&regs->mcr);
      reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
      reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
              FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
              FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
              FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
      netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
-     flexcan_write(reg_mcr, &regs->mcr);
+     priv->write(reg_mcr, &regs->mcr);
 
      /*
       * CTRL

@@ -879,7 +888,7 @@ static int flexcan_chip_start(struct net_device

*dev)

drivers/net/can/flexcan.c static int flexcan_chip_start(struct net_device

Quoted 9 lines

drivers/net/can/flexcan.c +1 -1

       * enable bus off interrupt
       * (== FLEXCAN_CTRL_ERR_STATE)
       */
-     reg_ctrl = flexcan_read(&regs->ctrl);
+     reg_ctrl = priv->read(&regs->ctrl);
      reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
      reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
              FLEXCAN_CTRL_ERR_STATE;

@@ -897,29 +906,29 @@ static int flexcan_chip_start(struct net_device

*dev)

Quoted 28 lines

drivers/net/can/flexcan.c +5 -7

      /* save for later use */
      priv->reg_ctrl_default = reg_ctrl;
      netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
-     flexcan_write(reg_ctrl, &regs->ctrl);
+     priv->write(reg_ctrl, &regs->ctrl);
 
      /* clear and invalidate all mailboxes first */
      for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
-             flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
+             priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
                            &regs->cantxfg[i].can_ctrl);
      }
 
      /* Errata ERR005829: mark first TX mailbox as INACTIVE */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
      /* mark TX mailbox as INACTIVE */
-     flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+     priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
                    &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
      /* acceptance mask/acceptance code (accept everything) */
-     flexcan_write(0x0, &regs->rxgmask);
-     flexcan_write(0x0, &regs->rx14mask);
-     flexcan_write(0x0, &regs->rx15mask);
+     priv->write(0x0, &regs->rxgmask);

drivers/net/can/flexcan.c static int flexcan_chip_start(struct net_device *dev)

Quoted 10 lines

drivers/net/can/flexcan.c +3 -2

+     priv->write(0x0, &regs->rx14mask);
+     priv->write(0x0, &regs->rx15mask);
 
      if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
-             flexcan_write(0x0, &regs->rxfgmask);
+             priv->write(0x0, &regs->rxfgmask);
 
      /*
       * On Vybrid, disable memory error detection interrupts @@
-934,16 +943,16 @@ static int flexcan_chip_start(struct net_device

*dev)

Quoted 5 lines

* and Correction of Memory Errors" to write to
* MECR register
*/

drivers/net/can/flexcan.c +1 -1

-             reg_crl2 = flexcan_read(&regs->crl2);
+             reg_crl2 = priv->read(&regs->crl2);

drivers/net/can/flexcan.c static int flexcan_chip_start(struct net_device *dev)

Quoted 10 lines

drivers/net/can/flexcan.c +3 -3

              reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
-             flexcan_write(reg_crl2, &regs->crl2);
+             priv->write(reg_crl2, &regs->crl2);
 
-             reg_mecr = flexcan_read(&regs->mecr);
+             reg_mecr = priv->read(&regs->mecr);
              reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
-             flexcan_write(reg_mecr, &regs->mecr);
+             priv->write(reg_mecr, &regs->mecr);
              reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ |

FLEXCAN_MECR_HANCEI_MSK |

drivers/net/can/flexcan.c static void flexcan_chip_stop(struct net_device

Quoted 21 lines

                              FLEXCAN_MECR_FANCEI_MSK);

drivers/net/can/flexcan.c +1 -1

-             flexcan_write(reg_mecr, &regs->mecr);
+             priv->write(reg_mecr, &regs->mecr);
      }
 
      err = flexcan_transceiver_enable(priv); @@ -958,11 +967,11 @@

static int flexcan_chip_start(struct net_device *dev)

      priv->can.state = CAN_STATE_ERROR_ACTIVE;

      /* enable FIFO interrupts */

drivers/net/can/flexcan.c +2 -2

-     flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+     priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 
      /* print chip status */
      netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
-                flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+                priv->read(&regs->mcr), priv->read(&regs->ctrl));
 
      return 0;

@@ -989,8 +998,8 @@ static void flexcan_chip_stop(struct net_device

*dev)

drivers/net/can/flexcan.c static int register_flexcandev(struct

Quoted 11 lines

drivers/net/can/flexcan.c +2 -2

      flexcan_chip_disable(priv);
 
      /* Disable all interrupts */
-     flexcan_write(0, &regs->imask1);
-     flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+     priv->write(0, &regs->imask1);
+     priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
                    &regs->ctrl);
 
      flexcan_transceiver_disable(priv);

@@ -1108,26 +1117,26 @@ static int register_flexcandev(struct

net_device *dev)

Quoted 4 lines

drivers/net/can/flexcan.c +0 -1

      err = flexcan_chip_disable(priv);
      if (err)
              goto out_disable_per;
-     reg = flexcan_read(&regs->ctrl);

drivers/net/can/flexcan.c static int register_flexcandev(struct net_device *dev)

Quoted 10 lines

drivers/net/can/flexcan.c +2 -1

+     reg = priv->read(&regs->ctrl);
      reg |= FLEXCAN_CTRL_CLK_SRC;
-     flexcan_write(reg, &regs->ctrl);
+     priv->write(reg, &regs->ctrl);
 
      err = flexcan_chip_enable(priv);
      if (err)
              goto out_chip_disable;
 
      /* set freeze, halt and activate FIFO, restrict register access

*/

Quoted 6 lines

drivers/net/can/flexcan.c +2 -2

-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
              FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
-     flexcan_write(reg, &regs->mcr);
+     priv->write(reg, &regs->mcr);

drivers/net/can/flexcan.c static int register_flexcandev(struct net_device *dev)

Quoted 10 lines

drivers/net/can/flexcan.c +1 -1

 
      /*
       * Currently we only support newer versions of this core
       * featuring a RX FIFO. Older cores found on some Coldfire
       * derivates are not yet supported.
       */
-     reg = flexcan_read(&regs->mcr);
+     reg = priv->read(&regs->mcr);
      if (!(reg & FLEXCAN_MCR_FEN)) {
              netdev_err(dev, "Could not enable RX FIFO, unsupported

core\n");

drivers/net/can/flexcan.c static int flexcan_probe(struct platform_device

Quoted 2 lines

drivers/net/can/flexcan.c +0 -0

              err = -ENODEV;

@@ -1183,6 +1192,8 @@ static int flexcan_probe(struct platform_device

*pdev)

drivers/net/can/flexcan.c static int flexcan_probe(struct platform_device *pdev)

Quoted 4 lines

drivers/net/can/flexcan.c +1 -0

      void __iomem *base;
      int err, irq;
      u32 clock_freq = 0;
+     /* Default case for most ARM based FSL SoC having BE FlexCAN IP

*/

drivers/net/can/flexcan.c static int flexcan_probe(struct platform_device *pdev) · line 1253

Quoted 11 lines

drivers/net/can/flexcan.c +1 -0

+     bool core_is_little = true, module_is_little = false;
 
      reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
      if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) @@ -1237,6 +1248,25

@@ static int flexcan_probe(struct platform_device *pdev)

      dev->flags |= IFF_ECHO;

      priv = netdev_priv(dev);

drivers/net/can/flexcan.c +3 -0

+
+     if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+             core_is_little = false;

Why not just using IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) directly ? (anyways, cpu_is_le seems a more appropriate name)

drivers/net/can/flexcan.c static int flexcan_probe(struct platform_device *pdev) · line 1256

Quoted 2 lines

drivers/net/can/flexcan.c +2 -0

+     if (of_property_read_bool(dev->dev.of_node, "little-endian"))
+             module_is_little = true;

Why that misleading name, instead of, eg. "chip_is_le" ?

Oh, and you'll expect explicitly set a new DTB attribute, if the chip is in LE - the default case.

Didn't you just say, you dont wanna break anything ?

Can you imagine that some people use DTB as a _board_ config (eg. in bootloader) instead of externalized kernel config ? ;-o

drivers/net/can/flexcan.c static int flexcan_probe(struct platform_device *pdev) · line 1268

Quoted 11 lines

drivers/net/can/flexcan.c +11 -0

+     if ((core_is_little && module_is_little) ||
+         (!core_is_little && !module_is_little)) {
+             priv->read = flexcan_read_le;
+             priv->write = flexcan_write_le;
+     }
+
+     if ((!core_is_little && module_is_little) ||
+         (core_is_little && !module_is_little)) {
+             priv->read = flexcan_read_be;
+             priv->write = flexcan_write_be;
+     }

At that point, the naming gets completely wrong - instead should be something like flexcan_read_swab / flexcan_write_swab. And the decision can easily be made on:

    IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) != module_is_little

Putting these together, I'd rather:

#1: add a new feature flag:

     #define FLEXCAN_HAS_BIG_ENDIAN BIT(4)

#2: add a new dts device type for the new chip variant
(eg. fsl,flexcan-qorliq)

#2: pass the priv pointer to the *_read()/*_write() functions,
so they can pick up the BE flag and decide whether to swab or not (based on cpu endianess)

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

-----Original Message-----
From: Marc Kleine-Budde [mailto:mkl at pengutronix.de]
Sent: Thursday, May 14, 2015 9:12 PM
To: Sharma Bhupesh-B45370; arnd at arndb.de; linux-can at vger.kernel.org
Cc: bhupesh.linux at gmail.com; Arora Sakar-B45205; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

Quoted 7 lines · Bhupesh Sharma

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Quoted 2 lines

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

The non FIFO mode doesn't guarantee the order of the incoming frames, not does not even try to...this is not acceptable. I'm currently working on a patch by David Jander that brings in non FIFO mode, but tries to keep the order of the frames.

-----Original Message-----
From: linux-arm-kernel [mailto:linux-arm-kernel-
bounces at lists.infradead.org] On Behalf Of Sharma Bhupesh
Sent: Thursday, May 14, 2015 9:14 PM
To: Marc Kleine-Budde; arnd at arndb.de; linux-can at vger.kernel.org
Cc: bhupesh.linux at gmail.com; linux-arm-kernel at lists.infradead.org; Arora Sakar-B45205
Subject: RE: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

Quoted 17 lines

-----Original Message-----
From: Marc Kleine-Budde [mailto:mkl at pengutronix.de]
Sent: Thursday, May 14, 2015 9:12 PM
To: Sharma Bhupesh-B45370; arnd at arndb.de; linux-can at vger.kernel.org
Cc: bhupesh.linux at gmail.com; Arora Sakar-B45205; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

Quoted 7 lines · Bhupesh Sharma

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Quoted 7 lines

Quoted 2 lines

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

The non FIFO mode doesn't guarantee the order of the incoming frames, not does not even try to...this is not acceptable. I'm currently working on a patch by David Jander that brings in non FIFO mode, but tries to keep the order of the frames.

That is already WIP at our end. V3 will contain the same change. If you are already working on it, I don't know how to proceed further as we had already v1 of this patchset with the non FIFO mode out since a month or so.

Hi Mark,

Quoted 2 lines

Quoted 2 lines

Subject: Re: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

I've just had to delve back into the deep murky past and try to get Freescale's Kernel 2.6.35 FlexCAN driver working. That's because the only code base that supports Freescale's Video Hardware is that one and we need working video.

I'm suggesting this code as an "historical reference" that might be useful for anyone looking for simple/simplistic ways to handle a FlexCAN port. It isn't like the driver actually works fully. It can't have ever been tested very much. Which is why I've had to fix it.

It has the Driver, Register handling and Message Buffer handling split into three separate source files, which is a useful simplification.

It can't be configured with "canconfig", but exposes a huge number of variables in the sysfs which is actually quite powerful and extendable.

Freescale's "2.6.35_maintain" kernel consists of 2.6.35 plus about 1200 Freescale patches which basically replace all the hardware drivers.

The source for this driver in this tree (until someone renames it to NXP):

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/log/?h=imx_2.6.35_maintain

The Driver is in the expected place:

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/net/can/flexcan?h=imx_2.6.35_maintain

1 - It defaults to 32 receive and 32 transmit MBs, but that can be changed.

2 - It can't receive in order, but you'd only need to sort on the timestamps to fix that (or use the FIFO).

3 - It can't transmit in order either (unless you drop it to one transmit MB), but a simple change to the Transmit MB assignment would fix that.

4 - It supports FIFO mode, but it doesn't work at all. The FIFO hardware gets so badly screwed by the driver that it has to be power-cycled to get it working again.

5 - Transmit doesn't work either. If you push it it'll start sending ONE Message per SECOND. That's an easy fix by changing the code to actually unblock the netif queue instead of what it does.

6 - The sysfs variable that reserves receive message buffers is named to reserve transmit buffers, it messes up if the DLC is over 8 (because it doesn't call get_can_dlc()), the Dump routines don't work properly, off-by-one bug, comparison-reversal bug and so on.

7 - The only good thing about it is that it doesn't use NAPI, so when fixed it doesn't drop messages when you try to use MMC/eMMC/ESDHC.

FIFO bug documented and fixed here:

https://community.freescale.com/thread/381075

Transmit bug documented and fixed here (and the other ones listed), also MMC/eMMC problem:

https://community.freescale.com/message/595897

Patches to fix all of it on the end of this thread:

https://community.freescale.com/thread/303271

Quoted 2 lines · Tom Evans

I've just had to delve back into the deep murky past and try to get Freescale's Kernel 2.6.35 FlexCAN driver working...

2.6.x I feel your pain. Another option would be to port the flexcan driver to that old kernel. But I'm getting off topic here :)

Quoted 2 lines

2 - It can't receive in order, but you'd only need to sort on the 3 - It can't transmit in order either (unless you drop it to one

In order reception is crucial.

Quoted 3 lines

Patches to fix all of it on the end of this thread:

https://community.freescale.com/thread/303271

If there's interest in working with this prehistoric kernel, why isn't there anyone that picks up all the patches and add them to a git repo.

fsl doesn't seem to care either, maybe unless you're using their newest product :(

Quoted 3 lines · Marc Kleine-Budde

Quoted 2 lines · Tom Evans

I've just had to delve back into the deep murky past and try to get Freescale's Kernel 2.6.35 FlexCAN driver working...

On an i.MX53. That's the last supported kernel Freescale ever released for that series of parts.

The simplest path was to fix the
simple and stupidly obvious bugs in the existing driver rather than add new complicated bugs.

Quoted 4 lines · Tom Evans

On 10/12/2015 11:44 PM, Marc Kleine-Budde wrote:

The simplest path was to fix the simple and stupidly obvious bugs in the existing driver rather than add new complicated bugs.

There seems to be no end of bugs in this driver. It is a lesson in something.

Quoted 25 lines

Quoted 17 lines

-----Original Message-----
From: Marc Kleine-Budde [mailto:mkl at pengutronix.de]
Sent: Thursday, May 14, 2015 9:12 PM
To: Sharma Bhupesh-B45370; arnd at arndb.de; linux-can at vger.kernel.org
Cc: bhupesh.linux at gmail.com; Arora Sakar-B45205; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

Quoted 7 lines · Bhupesh Sharma

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Quoted 7 lines

Quoted 2 lines

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

The non FIFO mode doesn't guarantee the order of the incoming frames, not does not even try to...this is not acceptable. I'm currently working on a patch by David Jander that brings in non FIFO mode, but tries to keep the order of the frames.

Quoted 4 lines

That is already WIP at our end. V3 will contain the same change. If you are already working on it, I don't know how to proceed further as we had already v1 of this patchset with the non FIFO mode out since a month or so.

I don't remember seeing a patch from you which supports non-FIFO mode for flexcan IP. Since we now have Freescale LS1021A chip out in the field on which the FIFO mode broken, we cannot use the upstream flexcan driver for enabling flexcan IP on these chips.

Do you still have plans to work on this? Or should I submit my v3 with in-order reception supported for rx frames.

-----Original Message-----
From: Marc Kleine-Budde [mailto:mkl at pengutronix.de]
Sent: Thursday, December 10, 2015 5:49 PM

Quoted 25 lines · Sharma Bhupesh

Quoted 25 lines

Quoted 24 lines

-----Original Message-----
From: Marc Kleine-Budde [mailto:mkl at pengutronix.de]
Sent: Thursday, May 14, 2015 9:12 PM
To: Sharma Bhupesh-B45370; arnd at arndb.de; linux-can at vger.kernel.org
Cc: bhupesh.linux at gmail.com; Arora Sakar-B45205; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2 5/5] can: flexcan: Add support for non RX-FIFO mode

Quoted 9 lines · Bhupesh Sharma

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

The non FIFO mode doesn't guarantee the order of the incoming frames, not does not even try to...this is not acceptable. I'm currently working on a patch by David Jander that brings in non FIFO mode, but tries to keep the order of the frames.

Quoted 6 lines

Quoted 4 lines

That is already WIP at our end. V3 will contain the same change. If you are already working on it, I don't know how to proceed further as we had already v1 of this patchset with the non FIFO mode out since a month or so.

I don't remember seeing a patch from you which supports non-FIFO mode

for flexcan IP.

Quoted 2 lines

Since we now have Freescale LS1021A chip out in the field on which the FIFO mode broken, we cannot use the upstream flexcan driver for

enabling flexcan IP on these chips.

Quoted 3 lines

Do you still have plans to work on this? Or should I submit my v3 with in-order reception supported for rx frames.

The problem is, that the current code triggers a ordering issue (at least on the imx6) in non FIFO mode. The frames are not received as the documentation states. If you have access, take a look at "SR# 1-4074792564 : CAN Ordering Issues". It seems the freescale support doesn't have much interest in confirming the issue, nor bringing us in touch with the people who have access to the IP core source to see what's going on.

If we have to rely on the timestamps the next logical step is to add sorting by timestamp to the rx-fifo implementation. I'll send a patch series of the current state.

Quoted 3 lines

If we have to rely on the timestamps the next logical step is to add sorting by timestamp to the rx-fifo implementation. I'll send a patch series of the current state.

With my current v3, I see no rx-frame ordering issues atleast on LS1021A.

I can ask internally about more details on the "SR# 1-4074792564 : CAN Ordering Issues".

Quoted 9 lines · Bhupesh Sharma

This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver.

On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames.

Signed-off-by Bhupesh Sharma <[email protected]>

Signed-off-by Sakar Arora <[email protected]>

The non FIFO mode doesn't guarantee the order of the incoming frames, not does not even try to...this is not acceptable. I'm currently working on a patch by David Jander that brings in non FIFO mode, but tries to keep the order of the frames.

Marc