clk: si5351: Multisynth 6-7 fixes
cover clk: si5351: Multisynth 6-7 fixes
The second synthesis stage in the Si5351 clock generator consists of six *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* dividers (MS6 and MS7). The current si5351 driver implementation does not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 and 7. This patch series fixes that.
Patch 1 fixes the divider calculation for multisynth 6 and 7.
Patch 2 fixes the divider re-calculation for multisynth 6 and 7.
Info: Base on branch 'clk-fixes'.
Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recalc_rate for multisynth 6-7
drivers/clk/clk-si5351.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-)
Signature · 1 line
1.9.1
Michael Turquette
AppliedQuoting Sergej Sawazki (2015-05-11 01:44:19)
Quoted 15 lines
The second synthesis stage in the Si5351 clock generator consists of six *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* =
dividers (MS6 and MS7). The current si5351 driver implementation does not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 =
and 7. This patch series fixes that.
=Patch 1 fixes the divider calculation for multisynth 6 and 7. =
Patch 2 fixes the divider re-calculation for multisynth 6 and 7. =
Quoted 6 lines
Info: Base on branch 'clk-fixes'.
=Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recalc_rate for multisynth 6-7
Applied both patches to clk-next.
Regards,
Mike
Quoted 10 lines
=
drivers/clk/clk-si5351.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-)=
-- =
1.9.1
=20
Quoted 11 lines · Michael Turquette
Quoting Sergej Sawazki (2015-05-11 01:44:19)
Quoted 10 lines
The second synthesis stage in the Si5351 clock generator consists of six *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* dividers (MS6 and MS7). The current si5351 driver implementation does not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 and 7. This patch series fixes that.
Patch 1 fixes the divider calculation for multisynth 6 and 7.
Patch 2 fixes the divider re-calculation for multisynth 6 and 7.
Quoted 7 lines
Quoted 5 lines
Info: Base on branch 'clk-fixes'.
Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recalc_rate for multisynth 6-7Applied both patches to clk-next.
Sergei,
next time please _always_ keep the version numbering on your patches, IIRC it should be v3 and it should include the changelog history.
Also, I sent a Reviewed-by for at least the .round_rate callback patch. It would be nice if you'd include that into resends of your patch to help Mike keeping track of those.
Sebastian
Quoted 9 lines · On 15.05.2015 at 11:25 Sebastian Hesselbarth wrote:
Quoted 6 lines
Quoted 4 lines
Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recalc_rate for multisynth 6-7Applied both patches to clk-next.
Sergei,
Quoted 9 lines
next time please _always_ keep the version numbering on your patches, IIRC it should be v3 and it should include the changelog history.
Also, I sent a Reviewed-by for at least the .round_rate callback patch. It would be nice if you'd include that into resends of your patch to help Mike keeping track of those.
Sebastian
Sebastian, Mike,
sorry for the confusion. Next time I will be more careful.
Sergej