ARM: DRA7: add display support

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP.

As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled.

Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it.

So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5.

Signed-off-by Tomi Valkeinen <[email protected]>

---
  drivers/clk/ti/clk-7xx.c | 7 ++++++-
  1 file changed, 6 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +1 -1

index 2dd956b9affa..63b8323df918 100644
@@ -312,7 +312,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
  int __init dra7xx_dt_clk_init(void)
  {
  	int rc;
-	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;
 
  	ti_dt_clocks_register(dra7xx_clks);
 

Quoted 40 lines · Tomi Valkeinen

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP.

As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled.

Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it.

So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5.

Signed-off-by Tomi Valkeinen <[email protected]>

---
  drivers/clk/ti/clk-7xx.c | 7 ++++++-
  1 file changed, 6 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +1 -1

index 2dd956b9affa..63b8323df918 100644
@@ -312,7 +312,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
  int __init dra7xx_dt_clk_init(void)
  {
      int rc;
-    struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+    struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;
 
      ti_dt_clocks_register(dra7xx_clks);
 

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
      if (rc)
          pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 8 lines

drivers/clk/ti/clk-7xx.c +5 -0

+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
      return rc;
  }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

-Tero

Quoted 6 lines

Quoted 6 lines

drivers/clk/ti/clk-7xx.c +0 -0

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
      if (rc)
          pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 

Quoted 12 lines

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 8 lines

drivers/clk/ti/clk-7xx.c +5 -0

+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
      return rc;
  }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

Now that I sent this, I realize we only have support to set_parent / set_rate through the assigned-clock props, no enable. Any plans to extend this support Mike/Stephen?

Quoted 19 lines · Tero Kristo

Quoted 18 lines

Quoted 4 lines

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 10 lines

drivers/clk/ti/clk-7xx.c +5 -0

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
      if (rc)
          pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 
+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
      return rc;
  }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

Quoted 5 lines

Now that I sent this, I realize we only have support to set_parent / set_rate through the assigned-clock props, no enable. Any plans to extend this support Mike/Stephen?

Enable falls under the "critical clocks" discussion that is ongoing. I assume that this is some sort of critical clock that can't be turned off?

Quoted 2 lines

Enable falls under the "critical clocks" discussion that is ongoing. I assume that this is some sort of critical clock that can't be turned off?

It only needs to be enabled for this particular display IP subsystem to function:

http://marc.info/?l=linux-omap&m=142071550111482&w=2

I believe Tomi is taking this approach (enabling it unconditionally) to avoid adding support for a secondary IP block "main clock" to the hwmod

code. Apparently, the chips that contain this clock gating bit are not intended to be used for power-critical use cases, so there's not much motivation to switch it on and off with the display controller.

Quoted 19 lines

Quoted 18 lines

Quoted 4 lines

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 10 lines

drivers/clk/ti/clk-7xx.c +5 -0

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
      if (rc)
          pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 
+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
      return rc;
  }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

Quoted 5 lines

Now that I sent this, I realize we only have support to set_parent / set_rate through the assigned-clock props, no enable. Any plans to extend this support Mike/Stephen?

Enable falls under the "critical clocks" discussion that is ongoing. I assume that this is some sort of critical clock that can't be turned off?

Signature · 3 lines

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Quoting Stephen Boyd (2015-05-20 12:34:23)

Quoted 20 lines · Tero Kristo

Quoted 19 lines

Quoted 18 lines

Quoted 4 lines

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 10 lines

drivers/clk/ti/clk-7xx.c +5 -0

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
       if (rc)
           pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 
+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
       return rc;
   }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

Quoted 8 lines

Quoted 5 lines

Now that I sent this, I realize we only have support to set_parent / set_rate through the assigned-clock props, no enable. Any plans to extend this support Mike/Stephen?

Enable falls under the "critical clocks" discussion that is ongoing. I assume that this is some sort of critical clock that can't be turned off?

Just chiming in on the "critical clock" discussion. I'm not planning to merge something that lets Devicetree nodes call clk_enable on a clock. That's what drivers are for.

The assigned-rate and assigned-parent stuff that Tero mentioned is more like configuration data for a downstream clock consumer. Clock gating/ungating does not fall under this type of configuration data in my opinion.

I think that Tomi's patch to call clk_prepare_enable from dra7xx_dt_clk_init is a reasonable solution to the problem.

Regards,
Mike

Quoted 5 lines

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Quoted 9 lines · Michael Turquette

Just chiming in on the "critical clock" discussion. I'm not planning to merge something that lets Devicetree nodes call clk_enable on a clock. That's what drivers are for.

The assigned-rate and assigned-parent stuff that Tero mentioned is more like configuration data for a downstream clock consumer. Clock gating/ungating does not fall under this type of configuration data in my opinion.

Quoted 2 lines

I think that Tomi's patch to call clk_prepare_enable from dra7xx_dt_clk_init is a reasonable solution to the problem.

Yea, after this discussion I am fine with this approach also, seeing it apparently doesn't cause any ill side-effects.

Quoted 40 lines · Tomi Valkeinen

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP.

As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled.

Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it.

So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5.

Signed-off-by Tomi Valkeinen <[email protected]>

---
  drivers/clk/ti/clk-7xx.c | 7 ++++++-
  1 file changed, 6 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +1 -1

index 2dd956b9affa..63b8323df918 100644
@@ -312,7 +312,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
  int __init dra7xx_dt_clk_init(void)
  {
      int rc;
-    struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+    struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;
 
      ti_dt_clocks_register(dra7xx_clks);
 

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
      if (rc)
          pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 

drivers/clk/ti/clk-7xx.c int __init dra7xx_dt_clk_init(void) · line 357

Quoted 8 lines

drivers/clk/ti/clk-7xx.c +5 -0

+    hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+    rc = clk_prepare_enable(hdcp_ck);
+    if (rc)
+        pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
      return rc;
  }

You should rather use the assigned-clock properties in DT to accomplish this, the manual clock tweaks under the drivers/clk/ti/clk-* files should be converted to DT setup also.

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP.

As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled.

Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it.

So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5.

Signed-off-by Tomi Valkeinen <[email protected]>

---
 drivers/clk/ti/clk-7xx.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +6 -1

index 2dd956b9affa..63b8323df918 100644
@@ -312,7 +312,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 int __init dra7xx_dt_clk_init(void)
 {
        int rc;
-       struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+       struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;
 
        ti_dt_clocks_register(dra7xx_clks);
 

@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
        if (rc)
                pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 
+       hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+       rc = clk_prepare_enable(hdcp_ck);
+       if (rc)
+               pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
        return rc;
 }

Signature · 6 lines

2.1.4

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Hi,

This series adds the arch/arm/ side of the display support for DRA7 (DRA72x, DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards is added.

This series is v3, and is based on v4.1-rc2. There are no differences to v2, except rebased and tested.

Tomi

Tomi Valkeinen (10):
arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk
ARM: DRA7: hwmod: add DMM hwmod description
ARM: DRA7: hwmod: set DSS submodule parent hwmods
ARM: OMAP: display: change compat names to array
ARM: OMAP2+: display: detect DRA7 DSS
arm/dts: dra7.dtsi: add DSS support
arm/dts: dra72-evm.dts: add HDMI
arm/dts: am57xx-beagle-x15.dts: add HDMI
arm: dra7: add DESHDCP clock
CLK: TI: always enable DESHDCP clock

 arch/arm/boot/dts/am57xx-beagle-x15.dts   |  81 ++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi               |  43 ++++++++++++
 arch/arm/boot/dts/dra72-evm.dts           | 110 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra72x.dtsi             |  11 +++
 arch/arm/boot/dts/dra74x.dtsi             |  15 ++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi      |  11 +++
 arch/arm/mach-omap2/display.c             |  32 +++++----
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  33 +++++++++
 drivers/clk/ti/clk-7xx.c                  |   8 ++-
 9 files changed, 328 insertions(+), 16 deletions(-)

This series adds the arch/arm/ side of the display support for DRA7 (DRA72x, DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards is added.

This series is v3, and is based on v4.1-rc2. There are no differences to v2, except rebased and tested.

Hi Tomi

Quoted 4 lines · Tomi Valkeinen

This series adds the arch/arm/ side of the display support for DRA7 (DRA72x, DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards is added.

Quoted 2 lines

This series is v3, and is based on v4.1-rc2. There are no differences to v2, except rebased and tested.

Are you still planning to move the DESHDCP clock enable to the beginning of the series to avoid the warnings, per:

http://www.spinics.net/lists/arm-kernel/msg410968.html

Also, not sure if you can arrange for someone at TI to send over a DRA7xx board for the testbed, but it would be nice to have a board to test these patches with, to avoid issues like the one mentioned in your E-mails...