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: MIPS: PCI: Add pre_enable hook, minor readability fixes

PATCH Superseded Joshua Kinard 1 participant 1 message May 25, 2015 MIPS

v2 of 3 Superseded Latest is v3 →

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PATCH v2 1/1 : MIPS: PCI: Add pre_enable hook, minor readability fixes

From: Joshua Kinard <[email protected]>

This patch adds a hook "pre_enable", to the core MIPS PCI code. It is used by the IP30 Port to setup the PCI resources prior to probing the BRIDGE and detecting available PCI devices. It also adds some minor whitespace to improve readability.

---
 arch/mips/sgi-ip27/ip27-xtalk.c |   87 +++++++++++++++++++++---------
 1 file changed, 61 insertions(+), 26 deletions(-)

This version corrects several issues detected by checkpatch.pl.

linux-mips-pci-pre_enable.patch

arch/mips/include/asm/pci.h +3 -0
index d969299..b51ccbd 100644
@@ -43,6 +43,9 @@ struct pci_controller {
 	   and XFree86. Eventually will be removed. */
 	unsigned int need_domain_info;
 
+	/* called in pcibios_enable_resources */
+	int (*pre_enable)(struct pci_controller *, struct pci_dev *, int);
+
 	int iommu;
 
 	/* Optional access methods for reading/writing the bus number
arch/mips/pci/pci.c +8 -2
index b8a0bf5..57031e2 100644
@@ -261,14 +261,19 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 	u16 cmd, old_cmd;
 	int idx;
 	struct resource *r;
+	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 
 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
 	old_cmd = cmd;
-	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
+	for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
 		/* Only set up the requested stuff */
-		if (!(mask & (1<<idx)))
+		if (!(mask & (1 << idx)))
 			continue;
 
+		if (hose->pre_enable)
+			if (hose->pre_enable(hose, dev, idx) < 0)
+				return -EINVAL;
+
 		r = &dev->resource[idx];
 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 			continue;
@@ -291,6 +296,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 		       pci_name(dev), old_cmd, cmd);
 		pci_write_config_word(dev, PCI_COMMAND, cmd);
 	}
+
 	return 0;
 }