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arm, imx6, i2c: add I2C4 for MX6DL

PATCH New Heiko Schocher 2 participants 2 messages May 18, 2015 – May 26, 2015

Subsystems (3)
Arm (32-bit) Arm i.MX and Layerscape I2C
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Heiko Schocher

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#0 lore raw

PATCH v3 1/1 arm, imx6, i2c: add I2C4 for MX6DL

add I2C4 modul for MX6DL based boards.

Signed-off-by Heiko Schocher <[email protected]>

---
checkpatch shows:
WARNING: line over 80 characters
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)

but the hole file is full of lines longer than80 characters, so I let this line in the old style ...

Changes in v2:
- add comment from Stefano Babic
- reworked patch on base of commit f8cb101e1e3f5
- follow up patch cleans up different define naming
Series-changes: 3
- add comment from Stefano Babic
- rebase against 3bfe3ce2a6e3b04da1

 arch/arm/cpu/armv7/mx6/clock.c           | 33 +++++++++++++++++++++-----------
 arch/arm/imx-common/i2c-mxv7.c           |  5 ++++-
 arch/arm/include/asm/arch-mx6/crm_regs.h |  2 ++
 arch/arm/include/asm/arch-mx6/imx-regs.h |  1 +
 drivers/i2c/mxc_i2c.c                    |  3 +++
 5 files changed, 32 insertions(+), 12 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +22 -11
index 055f44e..ae99945 100644
@@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
 	u32 reg;
 	u32 mask;
 
-	if (i2c_num > 2)
+	if (i2c_num > 3)
 		return -EINVAL;
-
-	mask = MXC_CCM_CCGR_CG_MASK
-		<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-	reg = __raw_readl(&imx_ccm->CCGR2);
-	if (enable)
-		reg |= mask;
-	else
-		reg &= ~mask;
-	__raw_writel(reg, &imx_ccm->CCGR2);
+	if (i2c_num < 3) {
+		mask = MXC_CCM_CCGR_CG_MASK
+			<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+			+ (i2c_num << 1));
+		reg = __raw_readl(&imx_ccm->CCGR2);
+		if (enable)
+			reg |= mask;
+		else
+			reg &= ~mask;
+		__raw_writel(reg, &imx_ccm->CCGR2);
+	} else {
+		mask = MXC_CCM_CCGR_CG_MASK
+			<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+		reg = __raw_readl(&imx_ccm->CCGR1);
+		if (enable)
+			reg |= mask;
+		else
+			reg &= ~mask;
+		__raw_writel(reg, &imx_ccm->CCGR1);
+	}
 	return 0;
 }
 #endif
arch/arm/imx-common/i2c-mxv7.c +4 -1
index f3a5c3f..ff72b1a 100644
@@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
 #ifdef I2C3_BASE_ADDR
 	(void *)I2C3_BASE_ADDR,
 #endif
+#ifdef I2C4_BASE_ADDR
+	(void *)I2C4_BASE_ADDR,
+#endif
 };
 
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 	      struct i2c_pads_info *p)
 {
arch/arm/include/asm/arch-mx6/crm_regs.h +2 -0
index 0592ce0..887d048 100644
@@ -592,6 +592,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK			(3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0
index 9a4ad8b..3d3d137 100644
@@ -277,6 +277,7 @@
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
drivers/i2c/mxc_i2c.c +3 -0
index 81adf6f..2949e52 100644
@@ -517,6 +517,9 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = {
 	{ 0, I2C1_BASE_ADDR },
 	{ 1, I2C2_BASE_ADDR },
 	{ 2, I2C3_BASE_ADDR },
+#if defined(CONFIG_MX6DL)
+	{ 3, I2C4_BASE_ADDR },
+#endif
 #elif defined(CONFIG_LS102XA)
 	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
Signature · 1 line
2.1.0
#1 lore raw

PATCH v3 1/1 arm, imx6, i2c: add I2C4 for MX6DL

Quoted 126 lines · Heiko Schocher

add I2C4 modul for MX6DL based boards.

Signed-off-by Heiko Schocher <[email protected]>

---
checkpatch shows:
WARNING: line over 80 characters
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)

but the hole file is full of lines longer than80 characters, so I let this line in the old style ...

Changes in v2:
- add comment from Stefano Babic
- reworked patch on base of commit f8cb101e1e3f5
- follow up patch cleans up different define naming
Series-changes: 3
- add comment from Stefano Babic
- rebase against 3bfe3ce2a6e3b04da1

 arch/arm/cpu/armv7/mx6/clock.c           | 33 +++++++++++++++++++++-----------
 arch/arm/imx-common/i2c-mxv7.c           |  5 ++++-
 arch/arm/include/asm/arch-mx6/crm_regs.h |  2 ++
 arch/arm/include/asm/arch-mx6/imx-regs.h |  1 +
 drivers/i2c/mxc_i2c.c                    |  3 +++
 5 files changed, 32 insertions(+), 12 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +22 -11
index 055f44e..ae99945 100644
@@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
 	u32 reg;
 	u32 mask;
 
-	if (i2c_num > 2)
+	if (i2c_num > 3)
 		return -EINVAL;
-
-	mask = MXC_CCM_CCGR_CG_MASK
-		<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-	reg = __raw_readl(&imx_ccm->CCGR2);
-	if (enable)
-		reg |= mask;
-	else
-		reg &= ~mask;
-	__raw_writel(reg, &imx_ccm->CCGR2);
+	if (i2c_num < 3) {
+		mask = MXC_CCM_CCGR_CG_MASK
+			<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+			+ (i2c_num << 1));
+		reg = __raw_readl(&imx_ccm->CCGR2);
+		if (enable)
+			reg |= mask;
+		else
+			reg &= ~mask;
+		__raw_writel(reg, &imx_ccm->CCGR2);
+	} else {
+		mask = MXC_CCM_CCGR_CG_MASK
+			<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+		reg = __raw_readl(&imx_ccm->CCGR1);
+		if (enable)
+			reg |= mask;
+		else
+			reg &= ~mask;
+		__raw_writel(reg, &imx_ccm->CCGR1);
+	}
 	return 0;
 }
 #endif
arch/arm/imx-common/i2c-mxv7.c +4 -1
index f3a5c3f..ff72b1a 100644
@@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
 #ifdef I2C3_BASE_ADDR
 	(void *)I2C3_BASE_ADDR,
 #endif
+#ifdef I2C4_BASE_ADDR
+	(void *)I2C4_BASE_ADDR,
+#endif
 };
 
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 	      struct i2c_pads_info *p)
 {
arch/arm/include/asm/arch-mx6/crm_regs.h +2 -0
index 0592ce0..887d048 100644
@@ -592,6 +592,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK			(3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0
index 9a4ad8b..3d3d137 100644
@@ -277,6 +277,7 @@
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
drivers/i2c/mxc_i2c.c +0 -0
index 81adf6f..2949e52 100644

drivers/i2c/mxc_i2c.c static struct mxc_i2c_bus mxc_i2c_buses[] = { · line 525

Quoted 9 lines
drivers/i2c/mxc_i2c.c +3 -0
@@ -517,6 +517,9 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = {
 	{ 0, I2C1_BASE_ADDR },
 	{ 1, I2C2_BASE_ADDR },
 	{ 2, I2C3_BASE_ADDR },
+#if defined(CONFIG_MX6DL)
+	{ 3, I2C4_BASE_ADDR },
+#endif
 #elif defined(CONFIG_LS102XA)
 	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines
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