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clk: mvebu: add missing CESA gate clk

PATCH New Boris Brezillon 3 participants 3 messages May 26, 2015 – Jun 3, 2015

Subsystems (3)
Device tree bindings Common clk Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support
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Boris Brezillon

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#0 lore raw

PATCH v2 1/1 clk: mvebu: add missing CESA gate clk

Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node.

Signed-off-by Boris Brezillon <[email protected]>

---
Hi,

Sorry for the noise, but since the changes in this patch are quite straightforward, I'm directly sending a v2 addressing Gregory's comments (instead of waiting for more reviews).

Best Regards,

Boris

Changes since v1:
- update the DT bindings doc
- change the clock name to be consistent with other SoCs

 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 1 +
 drivers/clk/mvebu/armada-370.c                                | 1 +
 2 files changed, 2 insertions(+)
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +1 -0
index 31c7c0c..660e649 100644
@@ -19,6 +19,7 @@ ID	Clock	Peripheral
 9	pex1	PCIe Cntrl 1
 15	sata0	SATA Host 0
 17	sdio	SDHCI Host
+23	crypto	CESA (crypto engine)
 25	tdm	Time Division Mplx
 28	ddr	DDR Cntrl
 30	sata1	SATA Host 0
drivers/clk/mvebu/armada-370.c +1 -0
index 756f0f3..c19fd77 100644
@@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
 	{ "pex1", "pex1_en", 9, 0 },
 	{ "sata0", NULL, 15, 0 },
 	{ "sdio", NULL, 17, 0 },
+	{ "crypto", NULL, 23, 0 },
 	{ "tdm", NULL, 25, 0 },
 	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
 	{ "sata1", NULL, 30, 0 },
Signature · 1 line
1.9.1
#1 lore raw

PATCH v2 1/1 clk: mvebu: add missing CESA gate clk

Hi Boris,

Quoted 6 lines · Boris Brezillon

Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node.

Signed-off-by Boris Brezillon <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>

Thanks,

Gregory

Quoted 44 lines

---
Hi,

Sorry for the noise, but since the changes in this patch are quite straightforward, I'm directly sending a v2 addressing Gregory's comments (instead of waiting for more reviews).

Best Regards,

Boris

Changes since v1:
- update the DT bindings doc
- change the clock name to be consistent with other SoCs

 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 1 +
 drivers/clk/mvebu/armada-370.c                                | 1 +
 2 files changed, 2 insertions(+)
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +1 -0
index 31c7c0c..660e649 100644
@@ -19,6 +19,7 @@ ID	Clock	Peripheral
 9	pex1	PCIe Cntrl 1
 15	sata0	SATA Host 0
 17	sdio	SDHCI Host
+23	crypto	CESA (crypto engine)
 25	tdm	Time Division Mplx
 28	ddr	DDR Cntrl
 30	sata1	SATA Host 0
drivers/clk/mvebu/armada-370.c +1 -0
index 756f0f3..c19fd77 100644
@@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
 	{ "pex1", "pex1_en", 9, 0 },
 	{ "sata0", NULL, 15, 0 },
 	{ "sdio", NULL, 17, 0 },
+	{ "crypto", NULL, 23, 0 },
 	{ "tdm", NULL, 25, 0 },
 	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },
 	{ "sata1", NULL, 30, 0 },
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Applied
#2 lore raw

PATCH v2 1/1 clk: mvebu: add missing CESA gate clk

Quoting Gregory CLEMENT (2015-05-26 05:47:12)

Quoted 8 lines

Hi Boris,

Quoted 5 lines · Boris Brezillon

Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node.

Quoted 4 lines
Quoted 1 line
Signed-off-by Boris Brezillon <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>

Applied.

Regards,
Mike

Quoted 57 lines

Thanks,

Gregory

Quoted 44 lines

---
Hi,

Sorry for the noise, but since the changes in this patch are quite straightforward, I'm directly sending a v2 addressing Gregory's comments (instead of waiting for more reviews).

Best Regards,

Boris

Changes since v1:
- update the DT bindings doc
- change the clock name to be consistent with other SoCs

 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 1 +
 drivers/clk/mvebu/armada-370.c                                | 1 +
 2 files changed, 2 insertions(+)
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +1 -0
index 31c7c0c..660e649 100644
@@ -19,6 +19,7 @@ ID  Clock   Peripheral
 9    pex1    PCIe Cntrl 1
 15   sata0   SATA Host 0
 17   sdio    SDHCI Host
+23   crypto  CESA (crypto engine)
 25   tdm     Time Division Mplx
 28   ddr     DDR Cntrl
 30   sata1   SATA Host 0
drivers/clk/mvebu/armada-370.c +1 -0
index 756f0f3..c19fd77 100644
@@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
      { "pex1", "pex1_en", 9, 0 },
      { "sata0", NULL, 15, 0 },
      { "sdio", NULL, 17, 0 },
+     { "crypto", NULL, 23, 0 },
      { "tdm", NULL, 25, 0 },
      { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
      { "sata1", NULL, 30, 0 },
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com