Add Sunxi NAND support to SPL

index 0035f6e..3361251 100644
@@ -65,7 +65,13 @@ int gen_check_sum(struct boot_file_head *head_p)
 
 #define SUN4I_SRAM_SIZE 0x7600	/* 0x7748+ is used by BROM */
 #define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
-#define BLOCK_SIZE 512
+
+/*
+ * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
+ * to a multiple of 8K, and rejects the image otherwise. MMC-images are fine
+ * with 512B blocks. To cater for both, align to the largest of the two.
+ */
+#define BLOCK_SIZE 0x2000
 
 struct boot_img {
 	struct boot_file_head header;

new file mode 100644
index 0000000..e288f36
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2015 Roy Spliet <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_H
+#define _SUNXI_DMA_H
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#include <asm/arch/dma_sun4i.h>
+#else
+#error "DMA definition not available for this architecture"
+#endif
+
+#endif /* _SUNXI_DMA_H */

68 lines not on this page · raw message

index c28ee05..e40d368 100644
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
 	u32 apb0_gate;		/* 0x68 apb0 module clock gating */
 	u32 apb1_gate;		/* 0x6c apb1 module clock gating */
 	u8 res4[0x10];
-	u32 nand_sclk_cfg;	/* 0x80 nand sub clock control */
+	u32 nand0_clk_cfg;	/* 0x80 nand sub clock control */
 	u32 ms_sclk_cfg;	/* 0x84 memory stick sub clock control */
 	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
 	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */

@@ -177,7 +177,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_ACE		16
 #define AHB_GATE_OFFSET_DLL		15
 #define AHB_GATE_OFFSET_SDRAM		14
-#define AHB_GATE_OFFSET_NAND		13
+#define AHB_GATE_OFFSET_NAND0		13
 #define AHB_GATE_OFFSET_MS		12
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10

index 04c6d58..7ba818f 100644
@@ -215,11 +215,14 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB0		24
 #define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_NAND1		12
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10
 #define AHB_GATE_OFFSET_MMC1		9
 #define AHB_GATE_OFFSET_MMC0		8
 #define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA		6
 #define AHB_GATE_OFFSET_SS		5
 
 /* ahb_gate1 offsets */

index c506b0a..a61934f 100644
@@ -42,7 +42,7 @@ struct sunxi_ccm_reg {
 	u32 clk_output_b;	/* 0x184 clk_output_a */
 	u8 reserved5[0x278];	/* 0x188 */
 
-	u32 nand0_clk_cfg0;	/* 0x400 nand0 clock configuration0 */
+	u32 nand0_clk_cfg;	/* 0x400 nand0 clock configuration0 */
 	u32 nand0_clk_cfg1;	/* 0x404 nand1 clock configuration */
 	u8 reserved6[0x08];	/* 0x408 */
 	u32 sd0_clk_cfg;	/* 0x410 sd0 clock configuration */

@@ -113,8 +113,12 @@ struct sunxi_ccm_reg {
 
 /* ahb_gate0 fields */
 /* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_NAND0		13
 #define AHB_GATE_OFFSET_MMC(x)		8
 
+/* ahb gate1 field */
+#define AHB_GATE_OFFSET_DMA		24
+
 /* apb1_gate fields */
 #define APB1_GATE_UART_SHIFT		16
 #define APB1_GATE_UART_MASK		(0xff << APB1_GATE_UART_SHIFT)

index 6718ae2..70f413f 100644
@@ -111,8 +111,10 @@ void s_init(void)
 #ifdef CONFIG_SPL_BUILD
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
+ *
+ * Unfortunately we can't check how SPL was loaded so assume it's
+ * always the first SD/MMC controller, unless it was explicitly
+ * stated that SPL is on nand flash.
  */
 u32 spl_boot_device(void)
 {

@@ -122,6 +124,12 @@ u32 spl_boot_device(void)
 	 * enabled build. It has many restrictions and can only boot over USB.
 	 */
 	return BOOT_DEVICE_BOARD;
+#elif defined(CONFIG_SPL_NAND_SUPPORT)
+	/*
+	 * This is compile time configuration informing SPL, that it
+	 * was loaded from nand flash.
+	 */
+	return BOOT_DEVICE_NAND;
 #else
 	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected

index 59d8210..2b49616 100644
@@ -156,6 +156,8 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 
+#define SUNXI_GPC_NAND		2
+
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
 

67 lines not on this page · raw message

index d9f7691..d5bed30 100644
@@ -22,6 +22,9 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
+#ifdef CONFIG_NAND_SUNXI
+#include <nand.h>
+#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/display.h>

@@ -315,6 +318,19 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+void board_nand_init(void)
+{
+	unsigned int pin;
+	static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
+
+	/* Configure AHB muxes to connect output pins with NAND controller */
+	for (pin = 0; pin < 16; pin++)
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
+
+	for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
+}
+
 void i2c_init_board(void)
 {
 #ifdef CONFIG_I2C0_ENABLE

273 lines not on this page · raw message

index ea079eb..a3c9408 100644
@@ -18,6 +18,7 @@
 #endif
 
 #define CONFIG_SUNXI_USB_PHYS	3
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
 
 /*
  * Include common sunxi configuration where most the settings are

index d257659..8e13df5 100644
@@ -19,6 +19,9 @@
 
 #define CONFIG_SUNXI_USB_PHYS	2
 
+/* \todo A13 only defines port 19, whereas A10s requires each of these */
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19}
+
 /*
  * Include common sunxi configuration where most the settings are
  */

index 56101a9..3d26ce8 100644
@@ -24,6 +24,8 @@
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_TIMER_CLK_FREQ		24000000
 
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
+
 /*
  * Include common sunxi configuration where most the settings are
  */

index 7111c63..cd33758 100644
@@ -20,6 +20,12 @@
 
 #define CONFIG_SUNXI_USB_PHYS	2
 
+#if defined(CONFIG_MACH_SUN8I_A23)
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18}
+#elif defined(CONFIG_MACH_SUN8I_A33)
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{16}
+#endif
+
 /*
  * Include common sunxi configuration where most the settings are
  */

index c8ebb54..cce0441 100644
@@ -106,8 +106,10 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
+#if !defined(CONFIG_SPL_NAND_SUPPORT)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
+#endif /* CONFIG_SPL_NAND_SUPPORT */
 #endif
 
 /* 4MB of malloc() pool */

@@ -324,6 +326,24 @@ extern int soft_i2c_gpio_scl;
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_NAND
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_NAND_SUNXI
+#define CONFIG_CMD_SPL_WRITE_SIZE		0x000400
+#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x008000
+
+/* \todo Make these parameterisable in kernel config ? */
+#define CONFIG_NAND_SUNXI_PAGE_SIZE		8192
+#define CONFIG_NAND_SUNXI_ECC_STEP		1024
+#define CONFIG_NAND_SUNXI_ECC_STRENGTH		40
+#define CONFIG_NAND_SUNXI_ADDR_CYCLES		5
+
+#ifndef CONFIG_NAND_SUNXI_GPC_PORTS
+#error "No NAND GPC ports defined, NAND unsupported"
+#endif
+#endif /* CONFIG_SPL_NAND_SUPPORT */
+
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV