ARM: dts: sun8i: Support USB hosts
cover ARM: dts: sun8i: Support USB hosts
Hi everyone,
Allwinner A23/A33 have 2 USB PHYs, 1 for OTG and 1 for a normal EHCI/OHCI USB host pair. This series adds support for EHCI/OHCI. The SoC also supports HSIC, however no boards actually use it, so this is not implemented yet.
Patch 1 adds a new compatible for sun8i-a23 usb phys. It differs from previous ones in just the number of phys and how reset controls are routed.
Patch 2 adds device nodes for USB PHYs and hosts for A23/A33.
Patch 3 enables the USB hosts on the SinA33 dev board. On this board, VBUS is always on.
It's probably too late for 4.2, but I'd still like to try and get this merged.
Regards
ChenYu
Chen-Yu Tsai (3):
phy: sun4i-usb: Add support for sun8i A23/A33
ARM: dts: sun8i: Add support for USB controllers on A23/A33
ARM: dts: sun8i: sina33: Enable USB hosts
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 2 ++ arch/arm/boot/dts/sun8i-a23-a33.dtsi | 34 ++++++++++++++++++++++ arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 13 +++++++++ drivers/phy/phy-sun4i-usb.c | 7 +++-- 4 files changed, 54 insertions(+), 2 deletions(-)
Signature · 1 line
2.1.4
PATCH 1/3 phy: sun4i-usb: Add support for sun8i A23/A33
A23/A33 have separate reset lines for each PHY, like on sun6i, but only 2 PHYs instead of 3. Add a new compatible for this.
There is also an HSIC PHY, but no hardware that uses it exists.
--- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 2 ++ drivers/phy/phy-sun4i-usb.c | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +2 -0
@@ -7,6 +7,7 @@ Required properties: * allwinner,sun5i-a13-usb-phy * allwinner,sun6i-a31-usb-phy * allwinner,sun7i-a20-usb-phy + * allwinner,sun8i-a23-usb-phy - reg : a list of offset + length pairs - reg-names : * "phy_ctrl"
@@ -17,6 +18,7 @@ Required properties: - clock-names : * "usb_phy" for sun4i, sun5i or sun7i * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i + * "usb0_phy", "usb1_phy" for sun8i-a23 - resets : a list of phandle + reset specifier pairs - reset-names : * "usb0_reset"
drivers/phy/phy-sun4i-usb.c +5 -2
@@ -239,7 +239,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)mutex_init (&data->mutex); -if (of_device_is_compatible (np,"allwinner,sun5i-a13-usb-phy" )) +if (of_device_is_compatible (np,"allwinner,sun5i-a13-usb-phy" ) || +of_device_is_compatible (np,"allwinner,sun8i-a23-usb-phy" )) data->num_phys =2 ;else data->num_phys =3 ;
@@ -250,7 +251,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)else data->disc_thresh =2 ; -if (of_device_is_compatible (np,"allwinner,sun6i-a31-usb-phy" )) +if (of_device_is_compatible (np,"allwinner,sun6i-a31-usb-phy" ) || +of_device_is_compatible (np,"allwinner,sun8i-a23-usb-phy" )) dedicated_clocks = true;else dedicated_clocks = false;
@@ -320,6 +322,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun5i-a13-usb-phy" }, { .compatible = "allwinner,sun6i-a31-usb-phy" }, { .compatible = "allwinner,sun7i-a20-usb-phy" }, + { .compatible = "allwinner,sun8i-a23-usb-phy" }, { }, };MODULE_DEVICE_TABLE (of, sun4i_usb_phy_of_match);
Signature · 1 line
2.1.4
PATCH 1/3 phy: sun4i-usb: Add support for sun8i A23/A33
Hi,
Quoted 6 lines · Chen-Yu Tsai
A23/A33 have separate reset lines for each PHY, like on sun6i, but only 2 PHYs instead of 3. Add a new compatible for this.
There is also an HSIC PHY, but no hardware that uses it exists.
Signed-off-by Chen-Yu Tsai <[email protected]>
Heh, I've pretty much written the exact same patch (not that it was much work):
https://github.com/jwrdegoede/linux-sunxi/commit/bc062354f5e0ec75047859d7c2ee3fa04594d29c
Note though that:
1) In order to get the disconnect threshold correct you also need:
https://github.com/jwrdegoede/linux-sunxi/commit/f7dabee14450cd93e6d0b01f4b6ab065a55955e3
2) This will only work properly for the A23 not for the A33 on the A33 the phyctl reg sits at a different offset, see:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/usb/host/sunxi_hci.c#L49
So I've written a separate patch (on top of the a23 one, to add control for the A33 phy:
https://github.com/jwrdegoede/linux-sunxi/commit/b4536a92ede3187450b0f1c27c11c1f80fc66fc8
Note I also have patches to add support for the musb on sun6i (no sram controller for the otg sram, needs reset controller poking) this also works for the a23, and a separate patch for the a33 which needs some special handling again.
So how to move forward with this? I believe that it is best if I finish my work on this and post a series to Felipe and Kishon to apply on top of the 2 still outstanding phy-sun4i-usb / musb-sunxi patches.
As for the dts patches, those I plan to bundle with the dts patches I already have pending for otg support for sunxi in general.
Does that work for you ?
Regards,
Hans
Quoted 58 lines
--- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 2 ++ drivers/phy/phy-sun4i-usb.c | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +2
-0@@ -7,6 +7,7 @@ Required properties: * allwinner,sun5i-a13-usb-phy * allwinner,sun6i-a31-usb-phy * allwinner,sun7i-a20-usb-phy + * allwinner,sun8i-a23-usb-phy - reg : a list of offset + length pairs - reg-names : * "phy_ctrl"@@ -17,6 +18,7 @@ Required properties: - clock-names : * "usb_phy" for sun4i, sun5i or sun7i * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i + * "usb0_phy", "usb1_phy" for sun8i-a23 - resets : a list of phandle + reset specifier pairs - reset-names : * "usb0_reset"drivers/phy/phy-sun4i-usb.c +5
-2@@ -239,7 +239,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)mutex_init (&data->mutex); -if (of_device_is_compatible (np,"allwinner,sun5i-a13-usb-phy" )) +if (of_device_is_compatible (np,"allwinner,sun5i-a13-usb-phy" ) || +of_device_is_compatible (np,"allwinner,sun8i-a23-usb-phy" )) data->num_phys =2 ;else data->num_phys =3 ;@@ -250,7 +251,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)else data->disc_thresh =2 ; -if (of_device_is_compatible (np,"allwinner,sun6i-a31-usb-phy" )) +if (of_device_is_compatible (np,"allwinner,sun6i-a31-usb-phy" ) || +of_device_is_compatible (np,"allwinner,sun8i-a23-usb-phy" )) dedicated_clocks = true;else dedicated_clocks = false;@@ -320,6 +322,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun5i-a13-usb-phy" }, { .compatible = "allwinner,sun6i-a31-usb-phy" }, { .compatible = "allwinner,sun7i-a20-usb-phy" }, + { .compatible = "allwinner,sun8i-a23-usb-phy" }, { }, };MODULE_DEVICE_TABLE (of, sun4i_usb_phy_of_match);
[linux-sunxi] Re: [PATCH 1/3] phy: sun4i-usb: Add support for sun8i A23/A33
Hi,
Quoted 27 lines · Hans de Goede
Hi,
Quoted 7 lines · Chen-Yu Tsai
A23/A33 have separate reset lines for each PHY, like on sun6i, but only 2 PHYs instead of 3. Add a new compatible for this.
There is also an HSIC PHY, but no hardware that uses it exists.
Signed-off-by Chen-Yu Tsai <[email protected]>Heh, I've pretty much written the exact same patch (not that it was much work):
https://github.com/jwrdegoede/linux-sunxi/commit/bc062354f5e0ec75047859d7c2ee3fa04594d29c
Note though that:
1) In order to get the disconnect threshold correct you also need:
https://github.com/jwrdegoede/linux-sunxi/commit/f7dabee14450cd93e6d0b01f4b6ab065a55955e3
2) This will only work properly for the A23 not for the A33 on the A33 the phyctl reg
sits at a different offset, see:
Quoted 5 lines
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/usb/host/sunxi_hci.c#L49
So I've written a separate patch (on top of the a23 one, to add control for the A33 phy:
https://github.com/jwrdegoede/linux-sunxi/commit/b4536a92ede3187450b0f1c27c11c1f80fc66fc8
Interesting... It seems to just work without the above 2 one my A33. Disconnect seems fine as well, though I've not done any stress testing.
Since you have much more experience with USB than I do, I leave this to you.
Quoted 5 lines
Note I also have patches to add support for the musb on sun6i (no sram controller for the
otg sram, needs reset controller poking) this also works for the a23, and a separate patch
for the a33 which needs some special handling again.
Yes, I've seen them in your sunxi-wip branch.
Quoted 5 lines
So how to move forward with this? I believe that it is best if I finish my work on this
and post a series to Felipe and Kishon to apply on top of the 2 still outstanding
phy-sun4i-usb / musb-sunxi patches.
IIRC those will not make 4.2.
Quoted 5 lines
As for the dts patches, those I plan to bundle with the dts patches I already have
pending for otg support for sunxi in general.Does that work for you ?
Yes. Thanks! I'll pick the patches from your branch to test, or just wait until you post them.
Regards
ChenYu
[linux-sunxi] Re: [PATCH 1/3] phy: sun4i-usb: Add support for sun8i A23/A33
Hi,
Quoted 36 lines · Chen-Yu Tsai
Hi,
Quoted 27 lines · Hans de Goede
Hi,
Quoted 7 lines · Chen-Yu Tsai
A23/A33 have separate reset lines for each PHY, like on sun6i, but only 2 PHYs instead of 3. Add a new compatible for this.
There is also an HSIC PHY, but no hardware that uses it exists.
Signed-off-by Chen-Yu Tsai <[email protected]>Heh, I've pretty much written the exact same patch (not that it was much work):
https://github.com/jwrdegoede/linux-sunxi/commit/bc062354f5e0ec75047859d7c2ee3fa04594d29c
Note though that:
1) In order to get the disconnect threshold correct you also need:
https://github.com/jwrdegoede/linux-sunxi/commit/f7dabee14450cd93e6d0b01f4b6ab065a55955e3
2) This will only work properly for the A23 not for the A33 on the A33 the phyctl reg
sits at a different offset, see:Quoted 5 lines
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/usb/host/sunxi_hci.c#L49
So I've written a separate patch (on top of the a23 one, to add control for the A33 phy:
https://github.com/jwrdegoede/linux-sunxi/commit/b4536a92ede3187450b0f1c27c11c1f80fc66fc8
Quoted 5 lines
Interesting... It seems to just work without the above 2 one my A33. Disconnect seems fine as well, though I've not done any stress testing.
Since you have much more experience with USB than I do, I leave this to you.
TBH I'm just duplicating what allwinner is doing here, so I'm not that much of an expert either. As for why things are working fine for you, likely the phy default settings are good enough in most cases. It could even be that the allwinner kernel code is wrong (although I remember having seen the same exceptions for A33 in the bootloader code), and that my version of the code is actually relying on the defaults being good enough.
In the end it boils down to just trusting that the allwinner code is doing the right thing.
Quoted 8 lines
Quoted 5 lines
Note I also have patches to add support for the musb on sun6i (no sram controller for the
otg sram, needs reset controller poking) this also works for the a23, and a separate patch
for the a33 which needs some special handling again.Yes, I've seen them in your sunxi-wip branch.
Quoted 7 lines
Quoted 5 lines
So how to move forward with this? I believe that it is best if I finish my work on this
and post a series to Felipe and Kishon to apply on top of the 2 still outstanding
phy-sun4i-usb / musb-sunxi patches.IIRC those will not make 4.2.
Right.
Quoted 8 lines
Quoted 5 lines
As for the dts patches, those I plan to bundle with the dts patches I already have
pending for otg support for sunxi in general.Does that work for you ?
Yes. Thanks! I'll pick the patches from your branch to test, or just wait until you post them.
Ok.
REgards,
Hans
Quoted 5 lines
Regards
ChenYu
PATCH 2/3 ARM: dts: sun8i: Add support for USB controllers on A23/A33
In reply to Chen-Yu TsaiA23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs, one for the USB OTG controller, one for the EHCI/OHCI pair. The latter may also support HSIC, though none of the available boards utilize this, so this is not supported yet.
--- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
arch/arm/boot/dts/sun8i-a23-a33.dtsi +34 -0
@@ -332,6 +332,40 @@ #size-cells = <0>; }; + usbphy: phy at 01c19400 { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>, <&usb_clk 9>; + clock-names = "usb0_phy", "usb1_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb at 01c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb at 01c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl at 01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>;
Signature · 1 line
2.1.4
PATCH 2/3 ARM: dts: sun8i: Add support for USB controllers on A23/A33
Hi,
Quoted 6 lines · Chen-Yu Tsai
A23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs, one for the USB OTG controller, one for the EHCI/OHCI pair. The latter may also support HSIC, though none of the available boards utilize this, so this is not supported yet.
Signed-off-by Chen-Yu Tsai <[email protected]>
Thanks, I've applied this one (minus the phy node which belongs in sun8i-a23.dtsi as it is a23 specific) to my sunxi-wip branch, and if it is ok with you I will take care of upstreaming this further.
Regards,
Hans
Quoted 50 lines
--- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)arch/arm/boot/dts/sun8i-a23-a33.dtsi +34
-0@@ -332,6 +332,40 @@ #size-cells = <0>; }; + usbphy: phy at 01c19400 { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>, <&usb_clk 9>; + clock-names = "usb0_phy", "usb1_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb at 01c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb at 01c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl at 01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>;
PATCH 2/3 ARM: dts: sun8i: Add support for USB controllers on A23/A33
Quoted 9 lines · Hans de Goede
Hi,
Quoted 6 lines · Chen-Yu Tsai
A23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs, one for the USB OTG controller, one for the EHCI/OHCI pair. The latter may also support HSIC, though none of the available boards utilize this, so this is not supported yet.
Quoted 6 lines
Quoted 1 line
Signed-off-by Chen-Yu Tsai <[email protected]>Thanks, I've applied this one (minus the phy node which belongs in
sun8i-a23.dtsias it is a23 specific) to my sunxi-wip branch, and if it is ok with you I will take care of upstreaming this further.
OK with me. Thanks!
ChenYu
Quoted 56 lines
Quoted 55 lines
--- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)arch/arm/boot/dts/sun8i-a23-a33.dtsi +34
-0@@ -332,6 +332,40 @@ #size-cells = <0>; }; + usbphy: phy at 01c19400 { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>, <&usb_clk 9>; + clock-names = "usb0_phy", "usb1_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb at 01c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb at 01c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl at 01c20800 {/* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>;
PATCH 3/3 ARM: dts: sun8i: sina33: Enable USB hosts
In reply to Chen-Yu TsaiThe Sina33 SDK board exposes the EHCI/OHCI USB host pair. VBUS for this port is always on and non-controllable.
--- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +13 -0
@@ -63,6 +63,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &lradc { vref-supply = <®_vcc3v0>; status = "okay";
@@ -113,6 +117,10 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; +&ohci0 { + status = "okay"; +}; + &pio { mmc0_cd_pin_sina33: mmc0_cd_pin at 0 { allwinner,pins = "PB4";
@@ -127,3 +135,8 @@ pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +};
Signature · 1 line
2.1.4