Add GPIO driver for Freescale Vybrid platform

PATCH Superseded Bhuvanchandra DV 3 participants 16 messages Jun 1, 2015 – Jun 8, 2015

Subsystems (5)

Arm (32-bit) USB Arm i.MX and Layerscape GPIO +1 more subsystems

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Bhuvanchandra DV

author

2015-06-01 13:07 UTC #0 lore raw

v3 cover Add GPIO driver for Freescale Vybrid platform

Changes since V2:
Add defconfig and device tree files list to Toradex boards maintainer file. Invert the logic for enabling the DSPI support.

Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support

Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio

 arch/arm/cpu/armv7/vf610/generic.c            |   7 ++
 arch/arm/dts/Makefile                         |   3 +
 arch/arm/dts/vf-colibri.dtsi                  |  21 ++++
 arch/arm/dts/vf.dtsi                          | 100 +++++++++++++++
 arch/arm/dts/vf500-colibri.dts                |  18 +++
 arch/arm/dts/vf610-colibri.dts                |  18 +++
 arch/arm/imx-common/iomux-v3.c                |  26 ++++
 arch/arm/include/asm/arch-vf610/clock.h       |   1 +
 arch/arm/include/asm/arch-vf610/crm_regs.h    |   4 +
 arch/arm/include/asm/arch-vf610/gpio.h        |  29 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   5 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h |  59 +++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h    |   6 +
 board/toradex/colibri_vf/MAINTAINERS          |   4 +
 board/toradex/colibri_vf/colibri_vf.c         | 106 ++++++++++++++++
 configs/colibri_vf_defconfig                  |   1 +
 configs/colibri_vf_dtb_defconfig              |   8 ++
 drivers/gpio/Kconfig                          |   7 ++
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-uclass.c                    |   1 +
 drivers/gpio/vybrid_gpio.c                    | 169 ++++++++++++++++++++++++++
 drivers/usb/host/ehci-vf.c                    |   8 ++
 include/configs/colibri_vf.h                  |  12 ++
 23 files changed, 614 insertions(+)
 create mode 100644 arch/arm/dts/vf-colibri.dtsi
 create mode 100644 arch/arm/dts/vf.dtsi
 create mode 100644 arch/arm/dts/vf500-colibri.dts
 create mode 100644 arch/arm/dts/vf610-colibri.dts
 create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h
 create mode 100644 configs/colibri_vf_dtb_defconfig
 create mode 100644 drivers/gpio/vybrid_gpio.c

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #1 lore raw

PATCH v3 1/11 dm: gpio: uclass: Add flag to control sequence numbering

Like SPI and I2C few GPIO controllers also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver to control device sequence numbering. By defalut the dev->r_seq for gpio_uclass will alwalys returns -1, which leads the gpio driver probe failure when using the driver with device trees.

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 drivers/gpio/gpio-uclass.c | 1 +
 1 file changed, 1 insertion(+)

drivers/gpio/gpio-uclass.c +1 -0

index 530bb3e..bf982b9 100644
@@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev)
 UCLASS_DRIVER(gpio) = {
 	.id		= UCLASS_GPIO,
 	.name		= "gpio",
+	.flags		= DM_UC_FLAG_SEQ_ALIAS,
 	.post_probe	= gpio_post_probe,
 	.pre_remove	= gpio_pre_remove,
 	.per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #2 lore raw

PATCH v3 2/11 dm: gpio: vf610: Add GPIO driver support

In reply to Bhuvanchandra DV

Add GPIO driver support to Freescale VF610

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/imx-common/iomux-v3.c             |  26 +++++
 arch/arm/include/asm/arch-vf610/gpio.h     |  29 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h |   5 +
 arch/arm/include/asm/imx-common/iomux-v3.h |   6 +
 drivers/gpio/Kconfig                       |   7 ++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/vybrid_gpio.c                 | 169 +++++++++++++++++++++++++++++
 7 files changed, 243 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h
 create mode 100644 drivers/gpio/vybrid_gpio.c

arch/arm/imx-common/iomux-v3.c +26 -0

index e88e6e2..7fb23dd 100644
@@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
 	reg |= (value << start_bit);
 	writel(reg, base + group * 4);
 }
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction)
+{
+	u32 reg;
+	/*
+	 * Only on Vybrid the input/output buffer enable flags
+	 * are part of the shared mux/conf register.
+	 */
+	reg = readl(base + (gpio << 2));
+
+	if (direction)
+		reg |= 0x2;
+	else
+		reg &= ~0x2;
+
+	writel(reg, base + (gpio << 2));
+}
+
+void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
+{
+	*gpio_state = readl(base + (gpio << 2)) &
+		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
+}
+#endif

arch/arm/include/asm/arch-vf610/gpio.h new file +29 -0

new file mode 100644
index 0000000..622b8f0
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_VF610_GPIO_H
+#define __ASM_ARCH_VF610_GPIO_H
+
+#define VYBRID_GPIO_COUNT		32
+#define VF610_GPIO_DIRECTION_IN	0x0
+#define VF610_GPIO_DIRECTION_OUT	0x1
+
+/* GPIO registers */
+struct vybrid_gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+};
+
+struct vybrid_gpio_platdata {
+	unsigned int chip;
+	u32 base;
+	const char *port_name;
+};
+#endif	/* __ASM_ARCH_VF610_GPIO_H */

arch/arm/include/asm/arch-vf610/imx-regs.h +5 -0

index 2021981..7df3b1e 100644
@@ -81,6 +81,11 @@
 #define VREG_DIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x0006D000)
 #define SRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006E000)
 #define CMU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF100)
 
 /* AIPS 1 */
 #define OCOTP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00025000)

arch/arm/include/asm/imx-common/iomux-v3.h +6 -0

index e0a49be..2581019 100644
@@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 */
 void imx_iomux_set_gpr_register(int group, int start_bit,
 					 int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+				u32 *gpio_state);
+#endif
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)

drivers/gpio/Kconfig +7 -0

index 0840a30..0c43777 100644
@@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT
 	  are specified using the device tree. But you can also have a number
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
+
+config VYBRID_GPIO
+	bool "Vybrid GPIO driver"
+	depends on DM
+	default n
+	help
+	  Say yes here to support Vybrid vf610 GPIOs.

drivers/gpio/Makefile +1 -0

index ba9efe8..5864850 100644
@@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)	+= lpc32xx_gpio.o
 obj-$(CONFIG_STM32_GPIO)	+= stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
+obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o

drivers/gpio/vybrid_gpio.c new file +169 -0

169 lines not on this page · raw message

Signature · 1 line

2.1.0

Stefano Babic

2015-06-08 06:46 UTC #3 lore raw

PATCH v3 2/11 dm: gpio: vf610: Add GPIO driver support

Quoted 211 lines · Bhuvanchandra DV

Add GPIO driver support to Freescale VF610

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/imx-common/iomux-v3.c             |  26 +++++
 arch/arm/include/asm/arch-vf610/gpio.h     |  29 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h |   5 +
 arch/arm/include/asm/imx-common/iomux-v3.h |   6 +
 drivers/gpio/Kconfig                       |   7 ++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/vybrid_gpio.c                 | 169 +++++++++++++++++++++++++++++
 7 files changed, 243 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h
 create mode 100644 drivers/gpio/vybrid_gpio.c

arch/arm/imx-common/iomux-v3.c +26 -0

index e88e6e2..7fb23dd 100644
@@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
 	reg |= (value << start_bit);
 	writel(reg, base + group * 4);
 }
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction)
+{
+	u32 reg;
+	/*
+	 * Only on Vybrid the input/output buffer enable flags
+	 * are part of the shared mux/conf register.
+	 */
+	reg = readl(base + (gpio << 2));
+
+	if (direction)
+		reg |= 0x2;
+	else
+		reg &= ~0x2;
+
+	writel(reg, base + (gpio << 2));
+}
+
+void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
+{
+	*gpio_state = readl(base + (gpio << 2)) &
+		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
+}
+#endif

arch/arm/include/asm/arch-vf610/gpio.h new file +29 -0

new file mode 100644
index 0000000..622b8f0
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_VF610_GPIO_H
+#define __ASM_ARCH_VF610_GPIO_H
+
+#define VYBRID_GPIO_COUNT		32
+#define VF610_GPIO_DIRECTION_IN	0x0
+#define VF610_GPIO_DIRECTION_OUT	0x1
+
+/* GPIO registers */
+struct vybrid_gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+};
+
+struct vybrid_gpio_platdata {
+	unsigned int chip;
+	u32 base;
+	const char *port_name;
+};
+#endif	/* __ASM_ARCH_VF610_GPIO_H */

arch/arm/include/asm/arch-vf610/imx-regs.h +5 -0

index 2021981..7df3b1e 100644
@@ -81,6 +81,11 @@
 #define VREG_DIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x0006D000)
 #define SRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006E000)
 #define CMU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF100)
 
 /* AIPS 1 */
 #define OCOTP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00025000)

arch/arm/include/asm/imx-common/iomux-v3.h +6 -0

index e0a49be..2581019 100644
@@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 */
 void imx_iomux_set_gpr_register(int group, int start_bit,
 					 int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+				u32 *gpio_state);
+#endif
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)

drivers/gpio/Kconfig +7 -0

index 0840a30..0c43777 100644
@@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT
 	  are specified using the device tree. But you can also have a number
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
+
+config VYBRID_GPIO
+	bool "Vybrid GPIO driver"
+	depends on DM
+	default n
+	help
+	  Say yes here to support Vybrid vf610 GPIOs.

drivers/gpio/Makefile +1 -0

index ba9efe8..5864850 100644
@@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)	+= lpc32xx_gpio.o
 obj-$(CONFIG_STM32_GPIO)	+= stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
+obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o

drivers/gpio/vybrid_gpio.c new file +64 -0

new file mode 100644
index 0000000..6eaf0a9
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct vybrid_gpios {
+	unsigned int chip;
+	struct vybrid_gpio_regs *reg;
+};
+
+static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+	const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+	gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
+	imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN);
+
+	return 0;
+}
+
+static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio,
+					 int value)
+{
+	const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+	gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
+	gpio_set_value(gpio, value);
+	imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
+
+	return 0;
+}
+
+static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+	return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0;
+}
+
+static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio,
+				  int value)
+{
+	const struct vybrid_gpios *gpios = dev_get_priv(dev);
+	if (value)
+		writel((1 << gpio), &gpios->reg->gpio_psor);
+	else
+		writel((1 << gpio), &gpios->reg->gpio_pcor);
+
+	return 0;
+}
+

drivers/gpio/vybrid_gpio.c line 74

Quoted 10 lines

drivers/gpio/vybrid_gpio.c new file +10 -0

+static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+	const struct vybrid_gpios *gpios = dev_get_priv(dev);
+	u32 g_state = 0;
+
+	gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
+
+	imx_iomux_gpio_get_function(gpio, &g_state);
+
+	if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0)

Fixed by applying:

WARNING: line over 80 characters

#274: FILE: drivers/gpio/vybrid_gpio.c:74:
+ if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0)

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #4 lore raw

PATCH v3 3/11 colibri_vf: Add pinmux entries for GPIOs

In reply to Bhuvanchandra DV

Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.

Acked-by Stefan Agner <[email protected]>

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++
 board/toradex/colibri_vf/colibri_vf.c         | 60 +++++++++++++++++++++++++++
 2 files changed, 109 insertions(+)

arch/arm/include/asm/arch-vf610/iomux-vf610.h +49 -0

index 9226e69..e22e3f9 100644
@@ -32,22 +32,56 @@
 #define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
 				PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
 
+#define VF610_GPIO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
+
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA7__GPIO_134		= IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA17__GPIO_7			= IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA20__GPIO_10		= IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA21__GPIO_11		= IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA30__GPIO_20		= IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA31__GPIO_21		= IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB0__GPIO_22			= IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB1__GPIO_23			= IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTB5__UART1_RX		= IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB6__GPIO_28			= IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB7__GPIO_29			= IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB8__GPIO_30			= IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB9__GPIO_31			= IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTB10__UART0_TX		= IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTB11__UART0_RX		= IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB12__GPIO_34		= IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB13__GPIO_35		= IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB16__GPIO_38		= IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB17__GPIO_39		= IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB18__GPIO_40		= IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB21__GPIO_43		= IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB22__GPIO_44		= IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB23__GPIO_93		= IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB26__GPIO_96		= IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB28__GPIO_98		= IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC1__GPIO_46			= IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC1__RMII0_MDIO		= IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC0__GPIO_45			= IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC0__RMII0_MDC		= IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC2__RMII0_CRS_DV		= IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC2__GPIO_47			= IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC3__RMII0_RD1		= IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC3__GPIO_48			= IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC4__RMII0_RD0		= IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC4__GPIO_49			= IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC5__RMII0_RXER		= IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC5__GPIO_50			= IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC6__RMII0_TD1		= IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC6__GPIO_51			= IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC7__RMII0_TD0		= IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC7__GPIO_52			= IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC8__RMII0_TXEN		= IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC8__GPIO_53			= IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC10__RMII1_MDIO		= IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC9__RMII1_MDC		= IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC11__RMII1_CRS_DV		= IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -57,6 +91,8 @@ enum {
 	VF610_PAD_PTC15__RMII1_TD1		= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC16__RMII1_TD0		= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC17__RMII1_TXEN		= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC29__GPIO_102		= IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC30__GPIO_103		= IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTA24__ESDHC1_CLK		= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTA25__ESDHC1_CMD		= IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTA26__ESDHC1_DAT0		= IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),

@@ -66,13 +102,21 @@ enum {
 	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTD31__NF_IO15		= IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD31__GPIO_63		= IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD30__NF_IO14		= IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD30__GPIO_64		= IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD29__NF_IO13		= IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD29__GPIO_65		= IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD28__NF_IO12		= IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD28__GPIO_66		= IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD27__NF_IO11		= IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD27__GPIO_67		= IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD26__NF_IO10		= IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD26__GPIO_68		= IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD25__NF_IO9			= IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD25__GPIO_69		= IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD24__NF_IO8			= IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD24__GPIO_70		= IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD23__NF_IO7			= IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

@@ -83,9 +127,14 @@ enum {
 	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD8__QSPI0_B_CS0		= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD9__QSPI0_B_DATA3		= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__GPIO_88			= IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD10__QSPI0_B_DATA2		= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD10__GPIO_89		= IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD11__QSPI0_B_DATA1		= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD11__GPIO_90		= IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD12__QSPI0_B_DATA0		= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD12__GPIO_91		= IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD13__GPIO_92		= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD22__NF_IO6			= IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD21__NF_IO5			= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
 	VF610_PAD_PTD20__NF_IO4			= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

board/toradex/colibri_vf/colibri_vf.c +60 -0

72 lines not on this page · raw message

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #5 lore raw

PATCH v3 4/11 colibri_vf: Enable GPIO support

In reply to Bhuvanchandra DV

Acked-by Stefan Agner <[email protected]>

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 configs/colibri_vf_defconfig | 1 +
 include/configs/colibri_vf.h | 5 +++++
 2 files changed, 6 insertions(+)

configs/colibri_vf_defconfig +1 -0

index 3b1f66a..0715267 100644
@@ -3,3 +3,4 @@ CONFIG_TARGET_COLIBRI_VF=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_DM=y

include/configs/colibri_vf.h +5 -0

index 804291d..195102b 100644
@@ -54,6 +54,11 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
 
+/* GPIO support */
+#define CONFIG_DM_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_VYBRID_GPIO
+
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
 #define CONFIG_MTD_PARTITIONS

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #6 lore raw

PATCH v3 5/11 arm: vf610: Add clock support for DSPI

In reply to Bhuvanchandra DV

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/cpu/armv7/vf610/generic.c         | 7 +++++++
 arch/arm/include/asm/arch-vf610/clock.h    | 1 +
 arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++
 3 files changed, 12 insertions(+)

arch/arm/cpu/armv7/vf610/generic.c +7 -0

index 1bb9b8e..05c401d 100644
@@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)
 	return get_ipg_clk();
 }
 
+static u32 get_dspi_clk(void)
+{
+	return get_ipg_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {

@@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_fec_clk();
 	case MXC_I2C_CLK:
 		return get_i2c_clk();
+	case MXC_DSPI_CLK:
+		return get_dspi_clk();
 	default:
 		break;
 	}

arch/arm/include/asm/arch-vf610/clock.h +1 -0

index 535adad..e5a5c6d 100644
@@ -17,6 +17,7 @@ enum mxc_clock {
 	MXC_ESDHC_CLK,
 	MXC_FEC_CLK,
 	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
 };
 
 void enable_ocotp_clk(unsigned char enable);

arch/arm/include/asm/arch-vf610/crm_regs.h +4 -0

index bc6db2a..fdb45e9 100644
@@ -189,6 +189,8 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)

@@ -206,6 +208,8 @@ struct anadig_reg {
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
 #define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #7 lore raw

PATCH v3 6/11 arm: vf610: Add iomux support for DSPI

In reply to Bhuvanchandra DV

Add iomux definitions for DSPI second instance.

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/include/asm/arch-vf610/iomux-vf610.h |  9 +++++++++
 board/toradex/colibri_vf/colibri_vf.c         | 21 +++++++++++++++++++++
 2 files changed, 30 insertions(+)

arch/arm/include/asm/arch-vf610/iomux-vf610.h +9 -0

index e22e3f9..b8b22b1 100644
@@ -35,6 +35,11 @@
 #define VF610_GPIO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
 				PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
 
+#define VF610_DSPI_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -91,6 +96,10 @@ enum {
 	VF610_PAD_PTC15__RMII1_TD1		= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC16__RMII1_TD0		= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC17__RMII1_TXEN		= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTD5__DSPI1_CS0		= IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL),
+	VF610_PAD_PTD6__DSPI1_SIN		= IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL),
+	VF610_PAD_PTD7__DSPI1_SOUT		= IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL),
+	VF610_PAD_PTD8__DSPI1_SCK		= IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL),
 	VF610_PAD_PTC29__GPIO_102		= IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTC30__GPIO_103		= IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTA24__ESDHC1_CLK		= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),

board/toradex/colibri_vf/colibri_vf.c +21 -0

index e354c6d..7173022 100644
@@ -146,6 +146,20 @@ static void setup_iomux_nfc(void)
 }
 #endif
 
+#ifdef CONFIG_FSL_DSPI
+static void setup_iomux_dspi(void)
+{
+	static const iomux_v3_cfg_t dspi1_pads[] = {
+		VF610_PAD_PTD5__DSPI1_CS0,
+		VF610_PAD_PTD6__DSPI1_SIN,
+		VF610_PAD_PTD7__DSPI1_SOUT,
+		VF610_PAD_PTD8__DSPI1_SCK,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
+}
+#endif
+
 #ifdef CONFIG_VYBRID_GPIO
 static void setup_iomux_gpio(void)
 {

@@ -252,6 +266,9 @@ static void clock_init(void)
 
 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 			CCM_CCGR0_UART0_CTRL_MASK);
+#ifdef CONFIG_FSL_DSPI
+	setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
+#endif
 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 			CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,

@@ -364,6 +381,10 @@ int board_early_init_f(void)
 	setup_iomux_gpio();
 #endif
 
+#ifdef CONFIG_FSL_DSPI
+	setup_iomux_dspi();
+#endif
+
 	return 0;
 }

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #8 lore raw

PATCH v3 7/11 vf610: dts: Add device tree support

In reply to Bhuvanchandra DV

Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot.

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 arch/arm/dts/Makefile          |   3 ++
 arch/arm/dts/vf-colibri.dtsi   |  21 +++++++++
 arch/arm/dts/vf.dtsi           | 100 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/vf500-colibri.dts |  18 ++++++++
 arch/arm/dts/vf610-colibri.dts |  18 ++++++++
 5 files changed, 160 insertions(+)
 create mode 100644 arch/arm/dts/vf-colibri.dtsi
 create mode 100644 arch/arm/dts/vf.dtsi
 create mode 100644 arch/arm/dts/vf500-colibri.dts
 create mode 100644 arch/arm/dts/vf610-colibri.dts

arch/arm/dts/Makefile +3 -0

index 267fd17..55039df 100644
@@ -130,6 +130,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
 
+dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
+	vf610-colibri.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

arch/arm/dts/vf-colibri.dtsi new file +21 -0

new file mode 100644
index 0000000..7a8e9bee
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "vf.dtsi"
+
+&dspi1 {
+	status = "okay";
+	bus-num = <1>;
+
+	spi_cmd: sspi at 0 {
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};

arch/arm/dts/vf.dtsi new file +100 -0

100 lines not on this page · raw message

arch/arm/dts/vf500-colibri.dts new file +18 -0

new file mode 100644
index 0000000..e383306
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf-colibri.dtsi"
+
+/ {
+	model = "Toradex Colibri VF50";
+	compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500";
+};

arch/arm/dts/vf610-colibri.dts new file +18 -0

new file mode 100644
index 0000000..63bb3f4
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf-colibri.dtsi"
+
+/ {
+	model = "Toradex Colibri VF61";
+	compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610";
+};

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #9 lore raw

PATCH v3 8/11 colibri-vf: Enable SPI support

In reply to Bhuvanchandra DV

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 include/configs/colibri_vf.h | 7 +++++++
 1 file changed, 7 insertions(+)

include/configs/colibri_vf.h +7 -0

index 195102b..56e6d97 100644
@@ -272,4 +272,11 @@
 #define CONFIG_USB_GADGET_MASS_STORAGE
 #define CONFIG_CMD_USB_MASS_STORAGE
 
+/* Enable SPI support */
+#ifdef CONFIG_OF_CONTROL
+#define CONFIG_DM_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_FSL_DSPI
+#endif
+
 #endif /* __CONFIG_H */

Signature · 1 line

2.1.0

Stefan Agner

2015-06-01 17:04 UTC #10 lore raw

PATCH v3 8/11 colibri-vf: Enable SPI support

Quoted 11 lines · Bhuvanchandra DV

Signed-off-by Bhuvanchandra DV <[email protected]>
---
 include/configs/colibri_vf.h | 7 +++++++
 1 file changed, 7 insertions(+)
include/configs/colibri_vf.h +0 -0
index 195102b..56e6d97 100644
@@ -272,4 +272,11 @@
 #define CONFIG_USB_GADGET_MASS_STORAGE

include/configs/colibri_vf.h line 282

Quoted 10 lines

include/configs/colibri_vf.h +7 -0

 #define CONFIG_CMD_USB_MASS_STORAGE
 
+/* Enable SPI support */
+#ifdef CONFIG_OF_CONTROL
+#define CONFIG_DM_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_FSL_DSPI
+#endif
+
 #endif /* __CONFIG_H */

Thx,

Acked-by Stefan Agner <[email protected]>

--
Stefan

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #11 lore raw

PATCH v3 9/11 colibri_vf: Add separate defconfig for device tree support

In reply to Bhuvanchandra DV

Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.

Acked-by Stefan Agner <[email protected]>

Signed-off-by Bhuvanchandra DV <[email protected]>

---
 board/toradex/colibri_vf/MAINTAINERS | 4 ++++
 configs/colibri_vf_dtb_defconfig     | 8 ++++++++
 2 files changed, 12 insertions(+)
 create mode 100644 configs/colibri_vf_dtb_defconfig

board/toradex/colibri_vf/MAINTAINERS +4 -0

index 551c575..a1217a4 100644
@@ -4,3 +4,7 @@ S:	Maintained
 F:	board/toradex/colibri_vf/
 F:	include/configs/colibri_vf.h
 F:	configs/colibri_vf_defconfig
+F:	configs/colibri_vf_dtb_defconfig
+F:	arch/arm/dts/vf-colibri.dtsi
+F:	arch/arm/dts/vf500-colibri.dts
+F:	arch/arm/dts/vf610-colibri.dts

configs/colibri_vf_dtb_defconfig new file +8 -0

new file mode 100644
index 0000000..d4c8c58
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_TARGET_COLIBRI_VF=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #12 lore raw

PATCH v3 10/11 usb: ehci-vf: Add weak function for board specific initialisation

In reply to Bhuvanchandra DV

From: Sanchayan Maity <[email protected]>

Add a weak function board_ehci_hcd_init which can be used by the board file for board specific initialisation.

Signed-off-by Sanchayan Maity <[email protected]>

---
 drivers/usb/host/ehci-vf.c | 8 ++++++++
 1 file changed, 8 insertions(+)

drivers/usb/host/ehci-vf.c +8 -0

index 5454855..98e0fc6 100644
@@ -121,6 +121,11 @@ static void usb_oc_config(int index)
 	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
 }
 
+int __weak board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
 int ehci_hcd_init(int index, enum usb_init_type init,
 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {

@@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	ehci = (struct usb_ehci *)nc_reg_bases[index];
 
+	/* Do board specific initialisation */
+	board_ehci_hcd_init(index);
+
 	usb_power_config(index);
 	usb_oc_config(index);
 	usb_internal_phy_clock_gate(index);

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-01 13:07 UTC #13 lore raw

PATCH v3 11/11 colibri_vf: Enable board specific USB initialisation for USB pen gpio

In reply to Bhuvanchandra DV

From: Sanchayan Maity <[email protected]>

Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start".

Signed-off-by Sanchayan Maity <[email protected]>

---
 arch/arm/include/asm/arch-vf610/iomux-vf610.h |  1 +
 board/toradex/colibri_vf/colibri_vf.c         | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

arch/arm/include/asm/arch-vf610/iomux-vf610.h +1 -0

index b8b22b1..019307b 100644
@@ -131,6 +131,7 @@ enum {
 	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD4__GPIO_83         = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

board/toradex/colibri_vf/colibri_vf.c +25 -0

index 7173022..8618fd0 100644
@@ -20,6 +20,7 @@
 #include <netdev.h>
 #include <i2c.h>
 #include <g_dnl.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
 			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
 
+#define USB_PEN_GPIO           83
+
+static const iomux_v3_cfg_t usb_pads[] = {
+	VF610_PAD_PTD4__GPIO_83,
+};
+
 int dram_init(void)
 {
 	static const struct ddr3_jedec_timings timings = {

@@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 
 	return 0;
 }
+
+#ifdef CONFIG_USB_EHCI_VF
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+	switch (port) {
+	case 0:
+		/* USBC does not have PEN, also configured as USB client only */
+		break;
+	case 1:
+		gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
+		gpio_direction_output(USB_PEN_GPIO, 0);
+		break;
+	}
+	return 0;
+}
+#endif

Signature · 1 line

2.1.0

Bhuvanchandra DV

author

2015-06-08 06:09 UTC #14 lore raw

v3 cover Add GPIO driver for Freescale Vybrid platform

In reply to Bhuvanchandra DV

Hello Stefano,

Ping!

Quoted 43 lines · Bhuvanchandra DV

Changes since V2:
Add defconfig and device tree files list to Toradex boards maintainer file. Invert the logic for enabling the DSPI support.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio
  arch/arm/cpu/armv7/vf610/generic.c            |   7 ++
  arch/arm/dts/Makefile                         |   3 +
  arch/arm/dts/vf-colibri.dtsi                  |  21 ++++
  arch/arm/dts/vf.dtsi                          | 100 +++++++++++++++
  arch/arm/dts/vf500-colibri.dts                |  18 +++
  arch/arm/dts/vf610-colibri.dts                |  18 +++
  arch/arm/imx-common/iomux-v3.c                |  26 ++++
  arch/arm/include/asm/arch-vf610/clock.h       |   1 +
  arch/arm/include/asm/arch-vf610/crm_regs.h    |   4 +
  arch/arm/include/asm/arch-vf610/gpio.h        |  29 +++++
  arch/arm/include/asm/arch-vf610/imx-regs.h    |   5 +
  arch/arm/include/asm/arch-vf610/iomux-vf610.h |  59 +++++++++
  arch/arm/include/asm/imx-common/iomux-v3.h    |   6 +
  board/toradex/colibri_vf/MAINTAINERS          |   4 +
  board/toradex/colibri_vf/colibri_vf.c         | 106 ++++++++++++++++
  configs/colibri_vf_defconfig                  |   1 +
  configs/colibri_vf_dtb_defconfig              |   8 ++
  drivers/gpio/Kconfig                          |   7 ++
  drivers/gpio/Makefile                         |   1 +
  drivers/gpio/gpio-uclass.c                    |   1 +
  drivers/gpio/vybrid_gpio.c                    | 169 ++++++++++++++++++++++++++
  drivers/usb/host/ehci-vf.c                    |   8 ++
  include/configs/colibri_vf.h                  |  12 ++
  23 files changed, 614 insertions(+)

Quoted 8 lines

create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi
create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 configs/colibri_vf_dtb_defconfig create mode 100644 drivers/gpio/vybrid_gpio.c

Best regards,
Bhuvan

Stefano Babic

2015-06-08 06:47 UTC #15 lore raw

v3 cover Add GPIO driver for Freescale Vybrid platform

In reply to Bhuvanchandra DV

Quoted 42 lines · Bhuvanchandra DV

Changes since V2:
Add defconfig and device tree files list to Toradex boards maintainer file. Invert the logic for enabling the DSPI support.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio
 arch/arm/cpu/armv7/vf610/generic.c            |   7 ++
 arch/arm/dts/Makefile                         |   3 +
 arch/arm/dts/vf-colibri.dtsi                  |  21 ++++
 arch/arm/dts/vf.dtsi                          | 100 +++++++++++++++
 arch/arm/dts/vf500-colibri.dts                |  18 +++
 arch/arm/dts/vf610-colibri.dts                |  18 +++
 arch/arm/imx-common/iomux-v3.c                |  26 ++++
 arch/arm/include/asm/arch-vf610/clock.h       |   1 +
 arch/arm/include/asm/arch-vf610/crm_regs.h    |   4 +
 arch/arm/include/asm/arch-vf610/gpio.h        |  29 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   5 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h |  59 +++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h    |   6 +
 board/toradex/colibri_vf/MAINTAINERS          |   4 +
 board/toradex/colibri_vf/colibri_vf.c         | 106 ++++++++++++++++
 configs/colibri_vf_defconfig                  |   1 +
 configs/colibri_vf_dtb_defconfig              |   8 ++
 drivers/gpio/Kconfig                          |   7 ++
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-uclass.c                    |   1 +
 drivers/gpio/vybrid_gpio.c                    | 169 ++++++++++++++++++++++++++
 drivers/usb/host/ehci-vf.c                    |   8 ++
 include/configs/colibri_vf.h                  |  12 ++

Quoted 9 lines

 23 files changed, 614 insertions(+)
 create mode 100644 arch/arm/dts/vf-colibri.dtsi
 create mode 100644 arch/arm/dts/vf.dtsi
 create mode 100644 arch/arm/dts/vf500-colibri.dts
 create mode 100644 arch/arm/dts/vf610-colibri.dts
 create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h
 create mode 100644 configs/colibri_vf_dtb_defconfig
 create mode 100644 drivers/gpio/vybrid_gpio.c

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================