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arm: dts: vexpress: describe all PMUs in TC2 dts

PATCH New Mark Rutland 2 participants 2 messages Jun 11, 2015

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PATCH 1/1 arm: dts: vexpress: describe all PMUs in TC2 dts

The dts for the CoreTile Express A15x2 A7x3 (TC2) only describes the PMUs of the Cortex-A15 CPUs, and not the Cortex-A7 CPUs.

Now that we have a mechanism for describing disparate PMUs and their interrupts in device tree, this patch makes use of these to describe the PMUs for all CPUs in the system. For consistency, the existing A15 PMU interrupt-affinity property is reflowed across two lines.

Cc Liviu Dudau <[email protected]>
Cc Lorenzo Pieralisi <[email protected]>
Cc Sudeep Holla <[email protected]>
---
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

This was previously posted along with the corresponding support code [1], which is now queued in Will's perf/updates branch [2], for v4.2. I've rebased it atop of Sudeep's interrupt-affinity addition, but otherwise it's identical.

Liviu, Lorenzo, Sudeep, are you happy to ack this and/or queue it up to follow the support code?

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/343144.html
[2] https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/log/?h=perf/updates

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +13 -2
index 107395c..038e30e 100644
@@ -187,11 +187,22 @@
 			     <1 10 0xf08>;
 	};
 
-	pmu {
+	pmu_a15 {
 		compatible = "arm,cortex-a15-pmu";
 		interrupts = <0 68 4>,
 			     <0 69 4>;
-		interrupt-affinity = <&cpu0>, <&cpu1>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>;
+	};
+
+	pmu_a7 {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <0 128 4>,
+			     <0 129 4>,
+			     <0 130 4>;
+		interrupt-affinity = <&cpu2>,
+				     <&cpu3>,
+				     <&cpu4>;
 	};
 
 	oscclk6a: oscclk6a {
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PATCH 1/1 arm: dts: vexpress: describe all PMUs in TC2 dts

Quoted 17 lines · Mark Rutland

The dts for the CoreTile Express A15x2 A7x3 (TC2) only describes the PMUs of the Cortex-A15 CPUs, and not the Cortex-A7 CPUs.

Now that we have a mechanism for describing disparate PMUs and their interrupts in device tree, this patch makes use of these to describe the PMUs for all CPUs in the system. For consistency, the existing A15 PMU interrupt-affinity property is reflowed across two lines.

Cc Liviu Dudau <[email protected]>
Cc Lorenzo Pieralisi <[email protected]>
Cc Sudeep Holla <[email protected]>
---
  arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 15 +++++++++++++--
  1 file changed, 13 insertions(+), 2 deletions(-)
Quoted 6 lines

This was previously posted along with the corresponding support code [1], which is now queued in Will's perf/updates branch [2], for v4.2. I've rebased it atop of Sudeep's interrupt-affinity addition, but otherwise it's identical.

Liviu, Lorenzo, Sudeep, are you happy to ack this and/or queue it up to follow the support code?

Looks fine to me

Regards,
Sudeep