ARM: 8221/1: PJ4: allow building in Thumb-2 mode

From: Ard Biesheuvel <[email protected]>

Two files that get included when building the multi_v7_defconfig target fail to build when selecting THUMB2_KERNEL for this configuration.

In both cases, we can just build the file as ARM code, as none of its symbols are exported to modules, so there are no interworking concerns. In the iwmmxt.S case, add ENDPROC() declarations so the symbols are annotated as functions, resulting in the linker to emit the appropriate mode switches.

Acked-by Nicolas Pitre <[email protected]>

Tested-by Olof Johansson <[email protected]>

Signed-off-by Ard Biesheuvel <[email protected]>

Signed-off-by Russell King <[email protected]>

(cherry picked from commit 13d1b9575ac2c2da143cd2236b6cf0fc314570f8)

Cc <[email protected]> # v3.18+

Signed-off-by Kevin Hilman <[email protected]>

---
 arch/arm/kernel/Makefile |  1 +
 arch/arm/kernel/iwmmxt.S | 13 +++++++++++++
 2 files changed, 14 insertions(+)

arch/arm/kernel/Makefile +1 -0

index 03120e656aea..2ecc7d15bc09 100644
@@ -84,6 +84,7 @@ obj-$(CONFIG_CPU_PJ4B)                += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)           += iwmmxt.o
 obj-$(CONFIG_PERF_EVENTS)      += perf_regs.o
 obj-$(CONFIG_HW_PERF_EVENTS)   += perf_event.o perf_event_cpu.o
+CFLAGS_pj4-cp0.o               := -marm
 AFLAGS_iwmmxt.o                        := -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 

arch/arm/kernel/iwmmxt.S +13 -1

index ad58e565fe98..49fadbda8c63 100644
@@ -58,6 +58,7 @@
 #define MMX_SIZE               (0x98)
 
        .text
+       .arm
 
 /*
  * Lazy switching of Concan coprocessor context

@@ -182,6 +183,8 @@ concan_load:
        tmcr    wCon, r2
        ret     lr
 
+ENDPROC(iwmmxt_task_enable)
+
 /*
  * Back up Concan regs to save area and disable access to them
  * (mainly for gdb or sleep mode usage)

@@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable)
 1:     msr     cpsr_c, ip                      @ restore interrupt mode
        ldmfd   sp!, {r4, pc}
 
+ENDPROC(iwmmxt_task_disable)
+
 /*
  * Copy Concan state to given memory address
  *

@@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy)
        msr     cpsr_c, ip                      @ restore interrupt mode
        ret     r3
 
+ENDPROC(iwmmxt_task_copy)
+
 /*
  * Restore Concan state from given memory address
  *

@@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore)
        msr     cpsr_c, ip                      @ restore interrupt mode
        ret     r3
 
+ENDPROC(iwmmxt_task_restore)
+
 /*
  * Concan handling on task switch
  *

@@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch)
        mrc     p15, 0, r1, c2, c0, 0
        sub     pc, lr, r1, lsr #32             @ cpwait and return
 
+ENDPROC(iwmmxt_task_switch)
+
 /*
  * Remove Concan ownership of given task
  *

@@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release)
        msr     cpsr_c, r2                      @ restore interrupts
        ret     lr
 
+ENDPROC(iwmmxt_task_release)
+
        .data
 concan_owner:
        .word   0
--

2.3.1

Sasha,

Can you pick this one up for v3.18?

Your updated v3.18.y-queue builds fine now for all the arm/arm64 defconfigs except ARM multi_v7_defconfig + CONFIG_THUMB2_KERNEL=y, which this patch fixes.

Quoted 2 lines · Kevin Hilman

Sasha,

Quoted 5 lines

Can you pick this one up for v3.18?

Your updated v3.18.y-queue builds fine now for all the arm/arm64 defconfigs except ARM multi_v7_defconfig + CONFIG_THUMB2_KERNEL=y, which this patch fixes.

Sure. Thanks Kevin!

Hi Sasha,

Quoted 10 lines · Sasha Levin

Quoted 7 lines · Kevin Hilman

Sasha,

Can you pick this one up for v3.18?

Your updated v3.18.y-queue builds fine now for all the arm/arm64 defconfigs except ARM multi_v7_defconfig + CONFIG_THUMB2_KERNEL=y, which this patch fixes.

Quoted 2 lines

Sure. Thanks Kevin!

I'm still not seeing this one in v3.18.16 or in linux-3.18.y-queue, which results in build failures for some ARM defconfigs.

Kevin

P.S. If you want to peruse build/boot results for your linux-3.18.y-queue, you can find them here:
http://kernelci.org/job/stable-sasha/