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spi: cadence_qspi: sram depth from DT & fix for FIFO width

PATCH New Vikas Manocha 3 participants 11 messages Jun 10, 2015 – Jun 24, 2015

Subsystems (2)
Arm (32-bit) SPI
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Vikas Manocha

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#0 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

This patchset adds support to get controller sram size from device tree & fix to support different FIFO widths.

Vikas Manocha (3):
spi: cadence_qspi: move the sram partition in init
spi: cadence_qspi: get sram size from device tree
spi: cadence_qspi: support FIFO width other than 4 bytes

 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |   63 +++++++++++++++++-----------------------
 5 files changed, 31 insertions(+), 36 deletions(-)
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/3 spi: cadence_qspi: move the sram partition in init

There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization.

Signed-off-by Vikas Manocha <[email protected]>
---
 drivers/spi/cadence_qspi_apb.c |   16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)
drivers/spi/cadence_qspi_apb.c +5 -11
index 855e5c7..1924f3b 100644
@@ -38,10 +38,7 @@
 
 /* Controller sram size in word */
 #define CQSPI_REG_SRAM_SIZE_WORD		(128)
-#define CQSPI_REG_SRAM_RESV_WORDS		(2)
-#define CQSPI_REG_SRAM_PARTITION_WR		(1)
-#define CQSPI_REG_SRAM_PARTITION_RD		\
-	(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
+#define CQSPI_REG_SRAM_PARTITION_RD		(CQSPI_REG_SRAM_SIZE_WORD/2)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
 
 /* Transfer mode */

@@ -537,6 +534,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 	/* Configure the remap address register, no remap */
 	writel(0, plat->regbase + CQSPI_REG_REMAP);
 
+	/* Indirect mode configurations */
+	writel(CQSPI_REG_SRAM_PARTITION_RD,
+		plat->regbase + CQSPI_REG_SRAMPARTITION);
+
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 

@@ -698,10 +699,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 	/* Setup the indirect trigger address */
 	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-	/* Configure SRAM partition for read. */
-	writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
-	       CQSPI_REG_SRAMPARTITION);
-
 	/* Configure the opcode */
 	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 

@@ -798,9 +795,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 	/* Setup the indirect trigger address */
 	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-	writel(CQSPI_REG_SRAM_PARTITION_WR,
-	       plat->regbase + CQSPI_REG_SRAMPARTITION);
-
 	/* Configure the opcode */
 	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH 2/3 spi: cadence_qspi: get sram size from device tree

In reply to Vikas Manocha

sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by Vikas Manocha <[email protected]>
---
 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |    6 +-----
 5 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/dts/socfpga.dtsi +1 -0
index bf791c5..9b12420 100644
@@ -639,6 +639,7 @@
 			ext-decoder = <0>;  /* external decoder */
 			num-cs = <4>;
 			fifo-depth = <128>;
+			sram-size = <128>;
 			bus-num = <2>;
 			status = "disabled";
 		};
arch/arm/dts/stv0991.dts +1 -0
index 3b1efca..556df82 100644
@@ -35,6 +35,7 @@
 			ext-decoder = <0>; /* external decoder */
 			num-cs = <4>;
 			fifo-depth = <256>;
+			sram-size = <256>;
 			bus-num = <0>;
 			status = "okay";
drivers/spi/cadence_qspi.c +1 -0
index a75fc46..34a0f46 100644
@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
 	plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
 	plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+	plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
 	debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 	      __func__, plat->regbase, plat->ahbbase, plat->max_hz,
drivers/spi/cadence_qspi.h +1 -0
index c9a6142..98e57aa 100644
@@ -25,6 +25,7 @@ struct cadence_spi_platdata {
 	u32		tsd2d_ns;
 	u32		tchsh_ns;
 	u32		tslch_ns;
+	u32		sram_size;
 };
 
 struct cadence_spi_priv {
drivers/spi/cadence_qspi_apb.c +1 -5
index 1924f3b..5831905 100644
@@ -36,9 +36,6 @@
 
 #define CQSPI_FIFO_WIDTH			(4)
 
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD		(128)
-#define CQSPI_REG_SRAM_PARTITION_RD		(CQSPI_REG_SRAM_SIZE_WORD/2)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
 
 /* Transfer mode */

@@ -535,8 +532,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 	writel(0, plat->regbase + CQSPI_REG_REMAP);
 
 	/* Indirect mode configurations */
-	writel(CQSPI_REG_SRAM_PARTITION_RD,
-		plat->regbase + CQSPI_REG_SRAMPARTITION);
+	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
Signature · 1 line
1.7.9.5
author
#3 lore raw

PATCH 3/3 spi: cadence_qspi: support FIFO width other than 4 bytes

In reply to Vikas Manocha

This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops.

Signed-off-by Vikas Manocha <[email protected]>
---
 drivers/spi/cadence_qspi_apb.c |   47 ++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 23 deletions(-)
drivers/spi/cadence_qspi_apb.c +24 -23
index 5831905..a168912 100644
@@ -199,18 +199,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 	unsigned int *dest_ptr = (unsigned int *)dest;
 	unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 
-	while (remaining > 0) {
-		if (remaining >= CQSPI_FIFO_WIDTH) {
-			*dest_ptr = readl(src_ptr);
-			remaining -= CQSPI_FIFO_WIDTH;
-		} else {
-			/* dangling bytes */
-			temp = readl(src_ptr);
-			memcpy(dest_ptr, &temp, remaining);
-			break;
-		}
+	while (remaining >= sizeof(dest_ptr)) {
+		*dest_ptr = readl(src_ptr);
+		remaining -= sizeof(src_ptr);
 		dest_ptr++;
 	}
+	if (remaining) {
+		/* dangling bytes */
+		temp = readl(src_ptr);
+		memcpy(dest_ptr, &temp, remaining);
+	}
 
 	return;
 }

@@ -218,24 +216,27 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 	const void *src, unsigned int bytes)
 {
-	unsigned int temp;
+	unsigned int temp=0;
+	int i;
 	int remaining = bytes;
 	unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
 	unsigned int *src_ptr = (unsigned int *)src;
 
-	while (remaining > 0) {
-		if (remaining >= CQSPI_FIFO_WIDTH) {
-			writel(*src_ptr, dest_ptr);
-			remaining -= sizeof(unsigned int);
-		} else {
-			/* dangling bytes */
-			memcpy(&temp, src_ptr, remaining);
-			writel(temp, dest_ptr);
-			break;
-		}
-		src_ptr++;
+	while (remaining >= CQSPI_FIFO_WIDTH) {
+		for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
+			writel(*(src_ptr+i), dest_ptr+i);
+		src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
+		remaining -= CQSPI_FIFO_WIDTH;
+	}
+	if (remaining)
+	{
+		/* dangling bytes */
+		i = remaining/sizeof(dest_ptr);
+		memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
+		writel(temp, dest_ptr+i);
+		for (--i; i >= 0; i--)
+			writel(*(src_ptr+i), dest_ptr+i);
 	}
-
 	return;
 }
Signature · 1 line
1.7.9.5
author
#4 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

In reply to Vikas Manocha

Hi Stephen,
Any comments on the patchset.
Rgds,
Vikas

Quoted 27 lines

-----Original Message-----
From: Vikas MANOCHA
Sent: Tuesday, June 09, 2015 6:25 PM
To: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Cc: Vikas MANOCHA
Subject: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

This patchset adds support to get controller sram size from device tree & fix to support different FIFO widths.

Vikas Manocha (3):
spi: cadence_qspi: move the sram partition in init
spi: cadence_qspi: get sram size from device tree
spi: cadence_qspi: support FIFO width other than 4 bytes

 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |   63 +++++++++++++++++-------------------
----
 5 files changed, 31 insertions(+), 36 deletions(-)

--
1.7.9.5

#5 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 1 line · Vikas MANOCHA

Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then again.

Thanks,
Stefan

author
#6 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Stefan,

Quoted 8 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Quoted 7 lines

Hi Vikas,

Quoted 1 line · Vikas MANOCHA

Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Rgds,
Vikas

Quoted 3 lines

Thanks,
Stefan

#7 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 10 lines · Vikas MANOCHA
Quoted 10 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 7 lines
Quoted 5 lines · Vikas MANOCHA
Quoted 1 line

Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. And SPI NOR seems to work just fine with this one applied. Not errors and the write/read/compare test also works okay.

HTP.

Thanks,
Stefan

author
#8 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Thanks Stefan,
Adding Jagan to apply the patchset.
Rgds,
Vikas

Quoted 38 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Wednesday, June 24, 2015 3:09 AM
To: Vikas MANOCHA
Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 10 lines · Vikas MANOCHA
Quoted 10 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 7 lines
Quoted 5 lines · Vikas MANOCHA
Quoted 1 line

Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. And SPI NOR seems to work just fine with this one applied. Not errors and the write/read/compare test also works okay.

HTP.

Thanks,
Stefan

#9 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Quoted 2 lines · Vikas MANOCHA

Thanks Stefan,
Adding Jagan to apply the patchset.

I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check it those and resend.
Anyway I will apply these on master-next for next releases, is that fine?

Quoted 26 lines
Quoted 26 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Wednesday, June 24, 2015 3:09 AM
To: Vikas MANOCHA
Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 13 lines · Vikas MANOCHA
Quoted 13 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 1 line · Vikas MANOCHA

Any comments on the patchset.

Quoted 8 lines
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. And SPI NOR seems to work just fine with this one applied. Not errors and the write/read/compare test also works okay.

thanks!

Signature · 1 line
Jagan | openedev.
author
#10 lore raw

cover spi: cadence_qspi: sram depth from DT & fix for FIFO width

Thanks Jagan,

Quoted 8 lines

-----Original Message-----
From: Jagan Teki [mailto:jteki at openedev.com]
Sent: Wednesday, June 24, 2015 11:54 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot at lists.denx.de; grmoore at opensource.altera.com
Subject: Re: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Quoted 6 lines
Quoted 2 lines · Vikas MANOCHA

Thanks Stefan,
Adding Jagan to apply the patchset.

I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check it those and resend.

Yes for Patch3, I will fix it & send the v2.
Patch1 has one check info (Alignment should match open parenthesis) I think it should be ignored..

Rgds,
Vikas

Quoted 40 lines

Anyway I will apply these on master-next for next releases, is that fine?

Quoted 26 lines
Quoted 26 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Wednesday, June 24, 2015 3:09 AM
To: Vikas MANOCHA
Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 13 lines · Vikas MANOCHA
Quoted 13 lines

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot at lists.denx.de;
grmoore at opensource.altera.com; dinguyen at opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

Hi Vikas,

Quoted 1 line · Vikas MANOCHA

Any comments on the patchset.

Quoted 8 lines
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

I'll test them next week on a SoCFPGA based board and will comment then again.

Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. And SPI NOR seems to work just fine with this one applied. Not errors and the write/read/compare test also works okay.

thanks!
--
Jagan | openedev.