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ARM: socfpga: Add CPU_METHOD_OF_DECLARE for SoCFPGA

PATCH New dinh.linux at gmail.com 3 participants 6 messages Jun 3, 2015 – Jun 12, 2015

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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dinh.linux at gmail.com

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#0 lore raw

cover ARM: socfpga: Add CPU_METHOD_OF_DECLARE for SoCFPGA

From: Dinh Nguyen <[email protected]>

Hi Arnd, Kevin, Olof:

Please apply these 2 patches for v4.2. I could not do a pull request for these as they will cause a merge conflict for arm-soc/next.

Thanks,

Dinh Nguyen (2):
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

 arch/arm/mach-socfpga/core.h    |  3 ++-
 arch/arm/mach-socfpga/platsmp.c | 36 +++++++++++++++++++++++++++++++++++-
 arch/arm/mach-socfpga/socfpga.c |  1 -
 3 files changed, 37 insertions(+), 3 deletions(-)
Signature · 1 line
1.9.1.315.g3f09db0
author
#1 lore raw

PATCH 1/2 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5

From: Dinh Nguyen <[email protected]>

Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.

Signed-off-by Dinh Nguyen <[email protected]>
---
 arch/arm/mach-socfpga/core.h    | 1 -
 arch/arm/mach-socfpga/platsmp.c | 4 +++-
 arch/arm/mach-socfpga/socfpga.c | 1 -
 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-socfpga/core.h +0 -1
index 5913bbb..38e5cbf 100644
@@ -39,7 +39,6 @@ extern void socfpga_sysmgr_init(void);
 extern void __iomem *sys_manager_base_addr;
 extern void __iomem *rst_manager_base_addr;
 
-extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
 
 extern unsigned long socfpga_cpu1start_addr;
arch/arm/mach-socfpga/platsmp.c +3 -1
index 7886eae..b84c1a1 100644
@@ -83,10 +83,12 @@ static void socfpga_cpu_die(unsigned int cpu)
 		cpu_do_idle();
 }
 
-struct smp_operations socfpga_smp_ops __initdata = {
+static struct smp_operations socfpga_smp_ops __initdata = {
 	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,
 	.smp_boot_secondary	= socfpga_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= socfpga_cpu_die,
 #endif
 };
+
+CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
arch/arm/mach-socfpga/socfpga.c +0 -1
index b63dec6..a154920 100644
@@ -78,7 +78,6 @@ static const char *altera_dt_match[] = {
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 	.l2c_aux_val	= 0,
 	.l2c_aux_mask	= ~0,
-	.smp		= smp_ops(socfpga_smp_ops),
 	.init_irq	= socfpga_init_irq,
 	.restart	= socfpga_cyclone5_restart,
 	.dt_compat	= altera_dt_match,
Signature · 1 line
1.9.1.315.g3f09db0
author
#2 lore raw

PATCH 2/2 ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

In reply to dinh.linux at gmail.com

From: Dinh Nguyen <[email protected]>

Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences:

- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.

Signed-off-by Dinh Nguyen <[email protected]>
---
 arch/arm/mach-socfpga/core.h    |  2 ++
 arch/arm/mach-socfpga/platsmp.c | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
arch/arm/mach-socfpga/core.h +2 -0
index 38e5cbf..27e7c65 100644
@@ -25,6 +25,8 @@
 #define SOCFPGA_RSTMGR_MODPERRST	0x14
 #define SOCFPGA_RSTMGR_BRGMODRST	0x1c
 
+#define SOCFPGA_A10_RSTMGR_MODMPURST	0x20
+
 /* System Manager bits */
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
arch/arm/mach-socfpga/platsmp.c +32 -0
index b84c1a1..5454e9c 100644
@@ -54,6 +54,29 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	return 0;
 }
 
+static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+	if (socfpga_cpu1start_addr) {
+		writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
+		       SOCFPGA_A10_RSTMGR_MODMPURST);
+		memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+		writel(virt_to_phys(socfpga_secondary_startup),
+		       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
+
+		flush_cache_all();
+		smp_wmb();
+		outer_clean_range(0, trampoline_size);
+
+		/* This will release CPU #1 out of reset. */
+		writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
+	}
+
+	return 0;
+}
+
 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *np;

@@ -91,4 +114,13 @@ static struct smp_operations socfpga_smp_ops __initdata = {
 #endif
 };
 
+static struct smp_operations socfpga_a10_smp_ops __initdata = {
+	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,
+	.smp_boot_secondary	= socfpga_a10_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= socfpga_cpu_die,
+#endif
+};
+
 CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
+CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);
Signature · 1 line
1.9.1.315.g3f09db0
Applied
#3 lore raw

cover ARM: socfpga: Add CPU_METHOD_OF_DECLARE for SoCFPGA

In reply to dinh.linux at gmail.com
Quoted 6 lines · dinh.linux at gmail.com

From: Dinh Nguyen <[email protected]>

Hi Arnd, Kevin, Olof:

Please apply these 2 patches for v4.2. I could not do a pull request for these as they will cause a merge conflict for arm-soc/next.

Applied to socfpga/soc and merged into for-next without any conflicts.

For future reference, you could've added these to your previous branch (socfpga_updates_for_v4.2) and sent an additional pull request.

Kevin

#4 lore raw

cover ARM: socfpga: Add CPU_METHOD_OF_DECLARE for SoCFPGA

In reply to dinh.linux at gmail.com

Hi Dinh,

Quoted 4 lines · On Tue, Jun 2, 2015 at 7:14 PM, <[email protected]> wrote:

From: Dinh Nguyen <[email protected]>

Hi Arnd, Kevin, Olof:

Quoted 8 lines

Please apply these 2 patches for v4.2. I could not do a pull request for these as they will cause a merge conflict for arm-soc/next.

Thanks,

Dinh Nguyen (2):
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

This one caused a build failure after merging the L1 invalidate patch from Russell[1] since it removed the SoC specific secondary startup. I've fixed this up in our next/soc branch by using the generic secondary_startup[2]. Please let me know if you see any issues with this.

Kevin

[1] https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=next/cleanup&id=02b4e2756e01c623cc4dbceae4b07be75252db5b

[2] https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=socfpga/soc&id=89b8da06ba302dd130df60df7964ccd3ab151cd6

#5 lore raw

cover ARM: socfpga: Add CPU_METHOD_OF_DECLARE for SoCFPGA

Hi Kevin,

Quoted 22 lines · Kevin Hilman

Hi Dinh,

Quoted 4 lines · On Tue, Jun 2, 2015 at 7:14 PM, <[email protected]> wrote:

From: Dinh Nguyen <[email protected]>

Hi Arnd, Kevin, Olof:

Quoted 8 lines

Please apply these 2 patches for v4.2. I could not do a pull request for these as they will cause a merge conflict for arm-soc/next.

Thanks,

Dinh Nguyen (2):
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

This one caused a build failure after merging the L1 invalidate patch from Russell[1] since it removed the SoC specific secondary startup. I've fixed this up in our next/soc branch by using the generic secondary_startup[2]. Please let me know if you see any issues with this.

Quoted 6 lines

Kevin

[1] https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=next/cleanup&id=02b4e2756e01c623cc4dbceae4b07be75252db5b

[2] https://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/commit/?h=socfpga/soc&id=89b8da06ba302dd130df60df7964ccd3ab151cd6

Tested and not seeing any issues with your patch. Thanks for fixing it.

Dinh