i2c: omap: improve duty cycle on SCL

PATCH New Felipe Balbi 2 participants 8 messages Jun 16, 2015 – Jun 19, 2015

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I2C subsystem host drivers OMAP2+ support OMAP1 support OMAP I2C driver

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Felipe Balbi

author

2015-06-16 19:17 UTC #0 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.

One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.

The idea of the patch is simple:

calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.

tLow is calculated with a DIV_ROUND_UP() to make sure it's slightly higher than tHigh and to make sure that we end up within I2C specifications.

Kudos to Nishanth Menon and Dave Gerlach for helping debugging the TPS65218 problem found on AM437x SK.

Signed-off-by Felipe Balbi <[email protected]>

---
 drivers/i2c/busses/i2c-omap.c | 86 ++++++++++++++++++++++++++++---------------
 1 file changed, 56 insertions(+), 30 deletions(-)

drivers/i2c/busses/i2c-omap.c +56 ~~-30~~

index 4be54fa32839..01e343bd6d97 100644
@@ -29,6 +29,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/err.h>

@@ -44,6 +45,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/pinctrl/consumer.h>
 
+#define NSECS_PER_SEC			1000000000
+
 /* I2C controller revisions */
 #define OMAP_I2C_OMAP1_REV_2		0x20

@@ -347,6 +350,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 	unsigned long fclk_rate = 12000000;
 	unsigned long internal_clk = 0;
+	unsigned long internal_clk_period = 0;
+	unsigned long scl_period = 0;
 	struct clk *fclk;
 
 	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {

@@ -383,52 +388,73 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	}
 
 	if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
-
 		/*
 		 * HSI2C controller internal clk rate should be 19.2 Mhz for
-		 * HS and for all modes on 2430. On 34xx we can use lower rate
-		 * to get longer filter period for better noise suppression.
-		 * The filter is iclk (fclk for HS) period.
+		 * HS and for all modes on 2430. For all other devices and
+		 * speeds we will use a 12MHz internal clock.
 		 */
-		if (dev->speed > 400 ||
-			       dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
-			internal_clk = 19200;
-		else if (dev->speed > 100)
-			internal_clk = 9600;
-		else
-			internal_clk = 4000;
+		if (dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK ||
+				dev->speed > 400) {
+			internal_clk = 1920000;
+			internal_clk_period = NSECS_PER_SEC /
+				internal_clk; /* ns */
+		} else {
+			internal_clk = 12000000;
+			internal_clk_period = NSECS_PER_SEC /
+				internal_clk; /* ns */
+		}
+
 		fclk = clk_get(dev->dev, "fck");
-		fclk_rate = clk_get_rate(fclk) / 1000;
+		fclk_rate = clk_get_rate(fclk);
 		clk_put(fclk);
 
 		/* Compute prescaler divisor */
 		psc = fclk_rate / internal_clk;
 		psc = psc - 1;
 
+		/*
+		 * Here's the tricky part, we want to make sure our duty cycle
+		 * is as close to 50% as possible. In order to achieve that, we
+		 * will first figure out what's the period on chosen scl is,
+		 * then divide that by two and calculate SCLL and SCLH based on
+		 * that.
+		 *
+		 * SCLL and SCLH equations are as folows:
+		 *
+		 * SCLL = (tLow / iclk_period) - 7;
+		 * SCLH = (tHigh / iclk_period) - 5;
+		 *
+		 * Where iclk_period is period of Internal Clock.
+		 *
+		 * tLow and tHigh will be basically half of scl_period where
+		 * possible as long as we can match I2C spec's minimum limits
+		 * for them.
+		 */
+		scl_period = NSECS_PER_SEC / dev->speed;
+
 		/* If configured for High Speed */
 		if (dev->speed > 400) {
-			unsigned long scl;
+			unsigned long fs_period;
+
+			/*
+			 * first phase of HS mode is up to
+			 * 400kHz so we will use that.
+			 */
+			fs_period = NSECS_PER_SEC / 400;
 
 			/* For first phase of HS mode */
-			scl = internal_clk / 400;
-			fsscll = scl - (scl / 3) - 7;
-			fssclh = (scl / 3) - 5;
+			fsscll = DIV_ROUND_UP(fs_period >> 1,
+					internal_clk_period) - 7;
+			fssclh = (fs_period >> 1) / internal_clk_period - 5;
 
 			/* For second phase of HS mode */
-			scl = fclk_rate / dev->speed;
-			hsscll = scl - (scl / 3) - 7;
-			hssclh = (scl / 3) - 5;
-		} else if (dev->speed > 100) {
-			unsigned long scl;
-
-			/* Fast mode */
-			scl = internal_clk / dev->speed;
-			fsscll = scl - (scl / 3) - 7;
-			fssclh = (scl / 3) - 5;
-		} else {
-			/* Standard mode */
-			fsscll = internal_clk / (dev->speed * 2) - 7;
-			fssclh = internal_clk / (dev->speed * 2) - 5;
+			hsscll = DIV_ROUND_UP(scl_period >> 1,
+					internal_clk_period) - 7;
+			hssclh = (scl_period >> 1) / internal_clk_period - 5;
+		} else  {
+			fsscll = DIV_ROUND_UP(scl_period >> 1,
+					internal_clk_period) - 7;
+			fssclh = (scl_period >> 1) / internal_clk_period - 5;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;

Signature · 1 line

2.4.3

Felipe Balbi

author

2015-06-16 19:19 UTC #1 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Quoted 14 lines · Felipe Balbi

With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.

Quoted 8 lines

tLow is calculated with a DIV_ROUND_UP() to make sure it's slightly higher than tHigh and to make sure that we end up within I2C specifications.
Kudos to Nishanth Menon and Dave Gerlach for helping debugging the TPS65218 problem found on AM437x SK.
Signed-off-by Felipe Balbi <[email protected]>

the patch is correct, but I sent the version written on top of v3.14, I'll resend correct version, sorry.

Signature · 8 lines

balbi
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Michael Lawnick

2015-06-17 11:09 UTC #2 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

In reply to Felipe Balbi

Am 16.06.2015 um 21:17 schrieb Felipe Balbi:

Quoted 5 lines

With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.

Quoted 8 lines

One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.

...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?

Quoted 4 lines

PARAMETER                       SYMBOL  STANDARD-MODE   FAST-MODE     UNIT
                                          MIN. MAX.     MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s

Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?

Signature · 2 lines

KR
Michael

Felipe Balbi

author

2015-06-17 15:38 UTC #3 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Hi,

Quoted 17 lines · Michael Lawnick

Am 16.06.2015 um 21:17 schrieb Felipe Balbi:
Quoted 5 lines
With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
Quoted 8 lines
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.
...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?

Quoted 7 lines

Quoted 4 lines
PARAMETER SYMBOL STANDARD-MODE FAST-MODE UNIT
MIN. MAX. MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s
Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?

yes, tps is buggy, it's written in the commit log itself.

Signature · 8 lines

balbi
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Michael Lawnick

2015-06-18 06:39 UTC #4 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Am 17.06.2015 um 17:38 schrieb Felipe Balbi:

Quoted 25 lines

Hi,
Quoted 22 lines · Michael Lawnick
Am 16.06.2015 um 21:17 schrieb Felipe Balbi:
Quoted 5 lines
With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
Quoted 8 lines
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.
...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?
Quoted 4 lines
PARAMETER                       SYMBOL  STANDARD-MODE   FAST-MODE     UNIT
                                          MIN. MAX.     MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s

Quoted 5 lines

Quoted 2 lines
Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?
yes, tps is buggy, it's written in the commit log itself.

So I think it is unacceptable to change the adapters code violating specification because some buggy device doesn't work properly. This change for your device has chance to blow up many correctly working ones.

Signature · 2 lines

KR
Michael

Felipe Balbi

author

2015-06-18 17:24 UTC #5 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Quoted 26 lines · Michael Lawnick

Am 17.06.2015 um 17:38 schrieb Felipe Balbi:
Quoted 25 lines
Hi,
Quoted 22 lines · Michael Lawnick
Am 16.06.2015 um 21:17 schrieb Felipe Balbi:
Quoted 5 lines
With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
Quoted 8 lines
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.
...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?
Quoted 4 lines
PARAMETER SYMBOL STANDARD-MODE FAST-MODE UNIT
MIN. MAX. MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?
yes, tps is buggy, it's written in the commit log itself.
So I think it is unacceptable to change the adapters code violating specification because some buggy device doesn't work properly.

read the other thread and you'll see that it's not violating jack

Quoted 2 lines

This change for your device has chance to blow up many correctly working ones.

How ?

Signature · 8 lines

balbi
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Michael Lawnick

2015-06-19 05:41 UTC #6 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Am 18.06.2015 um 19:24 schrieb Felipe Balbi:

Quoted 36 lines · Michael Lawnick

Quoted 26 lines
Am 17.06.2015 um 17:38 schrieb Felipe Balbi:
Quoted 25 lines
Hi,
Quoted 22 lines · Michael Lawnick
Am 16.06.2015 um 21:17 schrieb Felipe Balbi:
Quoted 5 lines
With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
Quoted 8 lines
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.
...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?
Quoted 4 lines
PARAMETER                       SYMBOL  STANDARD-MODE   FAST-MODE     UNIT
                                          MIN. MAX.     MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?
yes, tps is buggy, it's written in the commit log itself.
So I think it is unacceptable to change the adapters code violating specification because some buggy device doesn't work properly.

Quoted 7 lines

read the other thread and you'll see that it's not violating jack
Quoted 2 lines
This change for your device has chance to blow up many correctly working ones.
How ?

The answer is so obvious that I'm a bit irritated.
Your patch description tells: 'and use 50% for tLow and 50% for tHigh' For 400kHz this means 1.25 us for high and low. This clearly violates the specification for minimum low period and will not work with any device that relies on it.
In the other thread it is discussed that your patch does effectively not do what you describe but this is something completely independent.

Signature · 2 lines

KR
Michael

Felipe Balbi

author

2015-06-19 15:30 UTC #7 lore raw

PATCH 1/1 i2c: omap: improve duty cycle on SCL

Quoted 39 lines · Michael Lawnick

Am 18.06.2015 um 19:24 schrieb Felipe Balbi:
Quoted 38 lines · Michael Lawnick
Quoted 26 lines
Am 17.06.2015 um 17:38 schrieb Felipe Balbi:
Quoted 25 lines
Hi,
Quoted 22 lines · Michael Lawnick
Am 16.06.2015 um 21:17 schrieb Felipe Balbi:
Quoted 5 lines
With this patch we try to be as close to 50% duty cycle as possible. The reason for this is that some devices present an erratic behavior with certain duty cycles.
Quoted 8 lines
One such example is TPS65218 PMIC which fails to change voltages when running @ 400kHz and duty cycle is lower than 34%.
The idea of the patch is simple:
calculate desired scl_period from requested scl and use 50% for tLow and 50% for tHigh.
...
Hmm, and what's about Philips I2C specification 2.1, Jan 2000, Table 5?
Quoted 4 lines
PARAMETER SYMBOL STANDARD-MODE FAST-MODE UNIT
MIN. MAX. MIN. MAX.
LOW period of the SCL clock     tLOW      4.7   ?       1.3   ?       ?s
HIGH period of the SCL clock    tHIGH     4.0   ?       0.6   ?       ?s
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Your signal is in spec (0.85 ?s high, 1,65 low). Maybe your TPS65218 is just buggy or signals are bad?
yes, tps is buggy, it's written in the commit log itself.
So I think it is unacceptable to change the adapters code violating specification because some buggy device doesn't work properly.
read the other thread and you'll see that it's not violating jack

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
This change for your device has chance to blow up many correctly working ones.
How ?
The answer is so obvious that I'm a bit irritated.
Your patch description tells: 'and use 50% for tLow and 50% for tHigh'

another one who can't do simple algebra.

http://marc.info/?l=linux-i2c&m=143456423512634&w=2
http://marc.info/?l=linux-i2c&m=143456444212698&w=2
http://marc.info/?l=linux-omap&m=143456762413953&w=2

Quoted 5 lines

For 400kHz this means 1.25 us for high and low. This clearly violates the specification for minimum low period and will not work with any device that relies on it.
In the other thread it is discussed that your patch does effectively not do what you describe but this is something completely independent.

Read the comment where the calculation goes, it states that we try to get as close to 50% duty cycle while making sure we're within spec.

Also, commit log is saying that we're using 50% of SCL period for tLow and tHigh calculation, not that duty cycle will be 50%, which it isn't.

Signature · 8 lines

balbi
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