ARM: mvebu: use DT properties to fine-tune the L2 configuration
PATCH 1/1 ARM: mvebu: use DT properties to fine-tune the L2 configuration
In order to optimize the L2 cache performance, this commit adjusts the configuration of the L2 on the Cortex-A9 based Marvell EBU processors (Armada 375, 38x and 39x), using the appropriate DT properties.
We enable double linefill, incr double linefill, data prefetch and disable double linefill on wrap. This matches the configuration that was fine tuned in the Marvell BSP.
---
Enabling the data prefetching depends on a patch from "Hauke Mehrtens <[email protected]>", [PATCH v4] ARM: l2c: add options to overwrite prefetching behavior, which has been applied by Russell (see
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8391/1)
but does not appear yet in his for-next branch.
--- arch/arm/boot/dts/armada-375.dtsi | 4 ++++ arch/arm/boot/dts/armada-38x.dtsi | 4 ++++ arch/arm/boot/dts/armada-39x.dtsi | 4 ++++ 3 files changed, 12 insertions(+)
arch/arm/boot/dts/armada-375.dtsi +4 -0
@@ -176,6 +176,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {
arch/arm/boot/dts/armada-38x.dtsi +4 -0
@@ -143,6 +143,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {
arch/arm/boot/dts/armada-39x.dtsi +4 -0
@@ -104,6 +104,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {
Signature · 1 line
2.1.0
PATCH 1/1 ARM: mvebu: use DT properties to fine-tune the L2 configuration
Hi Thomas,
Quoted 9 lines · Thomas Petazzoni
In order to optimize the L2 cache performance, this commit adjusts the configuration of the L2 on the Cortex-A9 based Marvell EBU processors (Armada 375, 38x and 39x), using the appropriate DT properties.
We enable double linefill, incr double linefill, data prefetch and disable double linefill on wrap. This matches the configuration that was fine tuned in the Marvell BSP.
Signed-off-by Thomas Petazzoni <[email protected]>
applied on mvebu/dt-4.3
Thanks,
Gregory
Quoted 58 lines
---
Enabling the data prefetching depends on a patch from "Hauke Mehrtens <[email protected]>", [PATCH v4] ARM: l2c: add options to overwrite prefetching behavior, which has been applied by Russell (see
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8391/1)
but does not appear yet in his for-next branch.--- arch/arm/boot/dts/armada-375.dtsi | 4 ++++ arch/arm/boot/dts/armada-38x.dtsi | 4 ++++ arch/arm/boot/dts/armada-39x.dtsi | 4 ++++ 3 files changed, 12 insertions(+)arch/arm/boot/dts/armada-375.dtsi +4
-0@@ -176,6 +176,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {arch/arm/boot/dts/armada-38x.dtsi +4
-0@@ -143,6 +143,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {arch/arm/boot/dts/armada-39x.dtsi +4
-0@@ -104,6 +104,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu at c000 {
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com