Add common clock support for Broadcom iProc architecture

Replace current device tree dummy clocks with real clock support for Broadcom Cygnus SoC

Signed-off-by Ray Jui <[email protected]>

Reviewed-by Scott Branden <[email protected]>

---
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   89 +++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 28 deletions(-)

arch/arm/boot/dts/bcm-cygnus-clock.dtsi +61 -28

index 60d8389..32bcd45 100644
@@ -36,56 +36,89 @@ clocks {
        ranges;
 
        osc: oscillator {
+               #clock-cells = <0>;
                compatible = "fixed-clock";
-               #clock-cells = <1>;
                clock-frequency = <25000000>;
        };
 
-       apb_clk: apb_clk {
-               compatible = "fixed-clock";
+       /* Cygnus ARM PLL */
+       armpll: armpll {
                #clock-cells = <0>;
-               clock-frequency = <1000000000>;
+               compatible = "brcm,cygnus-armpll";
+               clocks = <&osc>;
+               reg = <0x19000000 0x1000>;
        };
 
-       periph_clk: periph_clk {
-               compatible = "fixed-clock";
+       /* peripheral clock for system timer */
+       periph_clk: arm_periph_clk {
                #clock-cells = <0>;
-               clock-frequency = <500000000>;
+               compatible = "fixed-factor-clock";
+               clocks = <&armpll>;
+               clock-div = <2>;
+               clock-mult = <1>;
        };
 
-       sdio_clk: lcpll_ch2 {
-               compatible = "fixed-clock";
+       /* APB bus clock */
+       apb_clk: apb_clk {
                #clock-cells = <0>;
-               clock-frequency = <200000000>;
+               compatible = "fixed-factor-clock";
+               clocks = <&armpll>;
+               clock-div = <4>;
+               clock-mult = <1>;
        };
 
-       axi81_clk: axi81_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <100000000>;
+       genpll: genpll {
+               #clock-cells = <1>;
+               compatible = "brcm,cygnus-genpll";
+               reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
+               clocks = <&osc>;
+               clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
+                                    "enet_sw", "audio_125", "can";
        };
 
-       keypad_clk: keypad_clk {
-               compatible = "fixed-clock";
+       /* always 1/2 of the axi21 clock */
+       axi41_clk: axi41_clk {
                #clock-cells = <0>;
-               clock-frequency = <31806>;
+               compatible = "fixed-factor-clock";
+               clocks = <&genpll 1>;
+               clock-div = <2>;
+               clock-mult = <1>;
        };
 
-       adc_clk: adc_clk {
-               compatible = "fixed-clock";
+       /* always 1/4 of the axi21 clock */
+       axi81_clk: axi81_clk {
                #clock-cells = <0>;
-               clock-frequency = <1562500>;
+               compatible = "fixed-factor-clock";
+               clocks = <&genpll 1>;
+               clock-div = <4>;
+               clock-mult = <1>;
        };
 
-       pwm_clk: pwm_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1000000>;
+       lcpll0: lcpll0 {
+               #clock-cells = <1>;
+               compatible = "brcm,cygnus-lcpll0";
+               reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
+               clocks = <&osc>;
+               clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
+                                    "usb_phy", "smart_card", "ch5";
        };
 
-       lcd_clk: mipipll_ch1 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <100000000>;
+       mipipll: mipipll {
+               #clock-cells = <1>;
+               compatible = "brcm,cygnus-mipipll";
+               reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
+               clocks = <&osc>;
+               clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
+                                    "ch2_v3d", "ch3_unused", "ch4_unused",
+                                    "ch5_unused";
+       };
+
+       asiu_clks: asiu_clks {
+               #clock-cells = <1>;
+               compatible = "brcm,cygnus-asiu-clk";
+               reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
+
+               clocks = <&osc>;
+               clock-output-names = "keypad", "adc/touch", "pwm";
        };
 };

Signature · 1 line

1.7.9.5

Quoting Ray Jui (2015-05-05 11:13:22)

Quoted 5 lines

Replace current device tree dummy clocks with real clock support for Broadcom Cygnus SoC

Signed-off-by Ray Jui <[email protected]>

Reviewed-by Scott Branden <[email protected]>

Patches 1-4 & 6 are applied to clk-next. You can add my Ack to this patch:

Acked-by Michael Turquette <[email protected]>

arm-soc guys,

Any chance you can pick this up? Alternatively I can take it through the clk tree with an Ack.

This patchset contains the initial common clock support for Broadcom's iProc family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the basic reference clock for these PLLs. Each PLL may have several leaf clocks. One special group of clocks is the ASIU clocks, which are dervied directly from the crystal reference clock.

This patchset also contains the basic clock support for the Broadcom Cygnus SoC, which implements the iProc clock architecture

Changes from v6:
- Rebase to v4.1-rc2
- Consolidate iProc PLL and its leaf clocks into a single device node, based on feedback from Mike Turquette. The PLL and its leaf clocks are now exposed a clock consumer through indices of the same device node phandle
- Update iProc device tree binding document based on the above change
- Add SW override support to iProc PLL clocks

Changes from v5:
- Rebase to v4.0-rc4
- Drop of_clk_get_parent_rate helper function from the clock framework
- Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add standard clock set_rate and round_rate support and make use of DT properties "assigned-clocks" and "assigned-clock-rates" to initialize PLL to the desired rate when registering to the clock framework
- Add SW workaround for ASIC bug on MIPI PLL to always read back the same register following a write transaction, to ensure value is written to the correct register

Changes from v4:
- Add of_clk_get_parent_rate helper function into the clock framework
- Switch to use of_clk_get_parent_rate in the iProc PLL clock driver

Changes from v3:
- Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL and other iProc PLLs as clock provider. These PLLs have zero cells in DT and thefore of_clk_src_simple_get should be used instead
- Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been integrated into Cygnus revision B0 and has its core clock running off MIPI PLL Channel 2
- Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This allows us to derive 300 MHz V3D clock from channel 2 through the post divisor

Changes from v2:
- Re-arrange Cygnus clock/pll init functions so each init function is right next to its clock table
- Removed #defines for number of clocks in Cygnus. Have the number of clocks automatically determined based on array size of the clock table

Changes from v1:
- Separate drivers/clk/Makefile change for drivers/clk/bcm out to a standalone patch

Ray Jui (6):
clk: iproc: define Broadcom iProc clock binding
clk: iproc: add initial common clock support
clk: Change bcm clocks build dependency
clk: cygnus: add clock support for Broadcom Cygnus
ARM: dts: enable clock support for Broadcom Cygnus
clk: cygnus: remove Cygnus dummy clock binding

 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 -
 .../bindings/clock/brcm,iproc-clocks.txt           |  132 ++++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   89 ++-
 drivers/clk/Makefile                               |    2 +-
 drivers/clk/bcm/Kconfig                            |    9 +
 drivers/clk/bcm/Makefile                           |    2 +
 drivers/clk/bcm/clk-cygnus.c                       |  265 ++++++++
 drivers/clk/bcm/clk-iproc-armpll.c                 |  282 ++++++++
 drivers/clk/bcm/clk-iproc-asiu.c                   |  276 ++++++++
 drivers/clk/bcm/clk-iproc-pll.c                    |  716 ++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.h                        |  178 +++++
 include/dt-bindings/clock/bcm-cygnus.h             |   68 ++
 12 files changed, 1990 insertions(+), 63 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
 create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
 create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
 create mode 100644 drivers/clk/bcm/clk-iproc.h
 create mode 100644 include/dt-bindings/clock/bcm-cygnus.h

Hi Mike,

Have you had a chance to review the iProc clock patches? If possible, I'd like to get feedback from you as early as possible so I can make changes if required. It would be really nice if we can get the iProc clock patches going into v4.2.

A lot of our iProc drivers depend on these clock patches.

Thanks,

Ray

Quoted 83 lines · Ray Jui

This patchset contains the initial common clock support for Broadcom's iProc family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the basic reference clock for these PLLs. Each PLL may have several leaf clocks. One special group of clocks is the ASIU clocks, which are dervied directly from the crystal reference clock.

This patchset also contains the basic clock support for the Broadcom Cygnus SoC, which implements the iProc clock architecture

Changes from v6:
- Rebase to v4.1-rc2
- Consolidate iProc PLL and its leaf clocks into a single device node, based on feedback from Mike Turquette. The PLL and its leaf clocks are now exposed a clock consumer through indices of the same device node phandle
- Update iProc device tree binding document based on the above change
- Add SW override support to iProc PLL clocks

Changes from v5:
- Rebase to v4.0-rc4
- Drop of_clk_get_parent_rate helper function from the clock framework
- Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add standard clock set_rate and round_rate support and make use of DT properties "assigned-clocks" and "assigned-clock-rates" to initialize PLL to the desired rate when registering to the clock framework
- Add SW workaround for ASIC bug on MIPI PLL to always read back the same register following a write transaction, to ensure value is written to the correct register

Changes from v4:
- Add of_clk_get_parent_rate helper function into the clock framework
- Switch to use of_clk_get_parent_rate in the iProc PLL clock driver

Changes from v3:
- Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL and other iProc PLLs as clock provider. These PLLs have zero cells in DT and thefore of_clk_src_simple_get should be used instead
- Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been integrated into Cygnus revision B0 and has its core clock running off MIPI PLL Channel 2
- Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This allows us to derive 300 MHz V3D clock from channel 2 through the post divisor

Changes from v2:
- Re-arrange Cygnus clock/pll init functions so each init function is right next to its clock table
- Removed #defines for number of clocks in Cygnus. Have the number of clocks automatically determined based on array size of the clock table

Changes from v1:
- Separate drivers/clk/Makefile change for drivers/clk/bcm out to a standalone patch

Ray Jui (6):
clk: iproc: define Broadcom iProc clock binding
clk: iproc: add initial common clock support
clk: Change bcm clocks build dependency
clk: cygnus: add clock support for Broadcom Cygnus
ARM: dts: enable clock support for Broadcom Cygnus
clk: cygnus: remove Cygnus dummy clock binding

 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 -
 .../bindings/clock/brcm,iproc-clocks.txt           |  132 ++++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   89 ++-
 drivers/clk/Makefile                               |    2 +-
 drivers/clk/bcm/Kconfig                            |    9 +
 drivers/clk/bcm/Makefile                           |    2 +
 drivers/clk/bcm/clk-cygnus.c                       |  265 ++++++++
 drivers/clk/bcm/clk-iproc-armpll.c                 |  282 ++++++++
 drivers/clk/bcm/clk-iproc-asiu.c                   |  276 ++++++++
 drivers/clk/bcm/clk-iproc-pll.c                    |  716 ++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.h                        |  178 +++++
 include/dt-bindings/clock/bcm-cygnus.h             |   68 ++
 12 files changed, 1990 insertions(+), 63 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
 create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
 create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
 create mode 100644 drivers/clk/bcm/clk-iproc.h
 create mode 100644 include/dt-bindings/clock/bcm-cygnus.h

Hi Mike,

Have you had a chance to review the iProc clock patches? If possible, I'd like to get feedback from you as early as possible so I can make changes if required. It would be really nice if we can get the iProc clock patches going into v4.2.

A lot of our iProc drivers depend on these clock patches.

Thanks,

Ray

Quoted 83 lines · Ray Jui

This patchset contains the initial common clock support for Broadcom's iProc family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the basic reference clock for these PLLs. Each PLL may have several leaf clocks. One special group of clocks is the ASIU clocks, which are dervied directly from the crystal reference clock.

This patchset also contains the basic clock support for the Broadcom Cygnus SoC, which implements the iProc clock architecture

Changes from v6:
- Rebase to v4.1-rc2
- Consolidate iProc PLL and its leaf clocks into a single device node, based on feedback from Mike Turquette. The PLL and its leaf clocks are now exposed a clock consumer through indices of the same device node phandle
- Update iProc device tree binding document based on the above change
- Add SW override support to iProc PLL clocks

Changes from v5:
- Rebase to v4.0-rc4
- Drop of_clk_get_parent_rate helper function from the clock framework
- Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add standard clock set_rate and round_rate support and make use of DT properties "assigned-clocks" and "assigned-clock-rates" to initialize PLL to the desired rate when registering to the clock framework
- Add SW workaround for ASIC bug on MIPI PLL to always read back the same register following a write transaction, to ensure value is written to the correct register

Changes from v4:
- Add of_clk_get_parent_rate helper function into the clock framework
- Switch to use of_clk_get_parent_rate in the iProc PLL clock driver

Changes from v3:
- Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL and other iProc PLLs as clock provider. These PLLs have zero cells in DT and thefore of_clk_src_simple_get should be used instead
- Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been integrated into Cygnus revision B0 and has its core clock running off MIPI PLL Channel 2
- Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This allows us to derive 300 MHz V3D clock from channel 2 through the post divisor

Changes from v2:
- Re-arrange Cygnus clock/pll init functions so each init function is right next to its clock table
- Removed #defines for number of clocks in Cygnus. Have the number of clocks automatically determined based on array size of the clock table

Changes from v1:
- Separate drivers/clk/Makefile change for drivers/clk/bcm out to a standalone patch

Ray Jui (6):
clk: iproc: define Broadcom iProc clock binding
clk: iproc: add initial common clock support
clk: Change bcm clocks build dependency
clk: cygnus: add clock support for Broadcom Cygnus
ARM: dts: enable clock support for Broadcom Cygnus
clk: cygnus: remove Cygnus dummy clock binding

 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 -
 .../bindings/clock/brcm,iproc-clocks.txt           |  132 ++++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   89 ++-
 drivers/clk/Makefile                               |    2 +-
 drivers/clk/bcm/Kconfig                            |    9 +
 drivers/clk/bcm/Makefile                           |    2 +
 drivers/clk/bcm/clk-cygnus.c                       |  265 ++++++++
 drivers/clk/bcm/clk-iproc-armpll.c                 |  282 ++++++++
 drivers/clk/bcm/clk-iproc-asiu.c                   |  276 ++++++++
 drivers/clk/bcm/clk-iproc-pll.c                    |  716 ++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.h                        |  178 +++++
 include/dt-bindings/clock/bcm-cygnus.h             |   68 ++
 12 files changed, 1990 insertions(+), 63 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
 create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
 create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
 create mode 100644 drivers/clk/bcm/clk-iproc.h
 create mode 100644 include/dt-bindings/clock/bcm-cygnus.h