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0pf-j2 (sh2-compatible open hardware) FPGA board support.

PATCH In review Rob Landley 5 participants 15 messages Jun 18, 2015 – Jun 27, 2015

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#0 lore raw

cover 0pf-j2 (sh2-compatible open hardware) FPGA board support.

Basic board support for the open processor foundation j2, an sh2-compatible open processor (built from BSD licesed VHDL) described in our Linuxcon Japan presentation a couple weeks back, which was covered by Linux Weekly News at
https://lwn.net/Articles/647636/ and our slides are at
http://events.linuxfoundation.org/sites/events/files/slides/Turtles%20all%20the%20way.pdf

The first patch adds the new files, the second touches existing files. This is just enough to boot to a serial prompt out of initramfs.

I'm aware there is... room for improvement. Yes I need to convert it to device tree. Yes I need to clean up whatever the interrupt controller is doing. Yes I need to fix the SPARSE_IRQ and GETTIMEOFFSET stuff. But it boots initramfs to a shell prompt, and I want to get that out there.

This is the smallest chunk I could chip out that boots to a shell prompt via initramfs and serial console. There are more drivers to come in future, but at the moment they're all too ugly for words.

If you want to try this yourself, you can get a Numato Mimas v2 board at
https://numato.com/fpga-boards/xilinx/spartan6/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram.html
download a bitstream and vmlinux image from the "developer" tab of 0pf.org, (yes, that's a zero, the Organgutan Protection Foundation predates the Open Processor Foundation, but our marketing guys are running with it and saying the zero stands for no licensing fees), and then presumably install them with the (sadly python 3) bitstream flasher tool at
https://numato.com/community/threads/mimas-v2-programming-in-linux.15/
(then stick the kernel on a fat formatted sdcard in a file called "vmlinux" and the bootloader should know what to do. These kernel patches haven't got an mmc driver (it was too ugly for words, so was ethernet, we'll get there) but the bootloader knows how to use it.

(We also have instructions for the spartan s6 avnet microboard if you have one of those lying around or order one from
http://www.em.avnet.com/en-us/design/drc/Pages/Xilinx-Spartan-6-FPGA-LX9-MicroBoard.aspx
but adding an sdcard to that requires a soldering iron. There are external 4-pin sdcard readers for like $4 but the power/ground/data pins in the header don't match up to the order mmc card readers want them, so you have to solder on extension wires to the reader so you can reorder them. The numato is cheaper _and_ has built-in sdcard. The avnet has built-in ethernet instead. The same kernel runs on both, only the bitstreams differ.)

There's a VHDL build on 0pf.org too, which _can_ build bitstreams if you can figure out how to install the Xilinx Webthing bitstream compiler. (Which is a free download but immensely ugly. I'm working on proper documentation for that, but the install process is outright eldrich. I'm also looking at people trying to make open source bitstream compilers that work, but at the moment that's "build a full linux distro with llvm or pcc" territory. Oh, and the VHDL build needs an sh2-elf compiler, not sh2-unknown-linux, because the symbol prefixes are different and the bootloader code is written for the elf ones, not the linux ones. I'm told the ELF spec was translated into japanese and the translation codepage switch changed punctation, which is why the _ vs . thing happened in superh. The has underscore vs does not have underscore is just ELF's fault.)

Toolchain to build kernel and userspace: the last code sourcery superh release worked with elf2flt, aboriginal linux's sh2eb target builds a working simple-cross-compiler also elf2flt, and the musl-libc.org have a working fdpic setup. (With a horrible hack in the specfile to _not_ build the kernel as pic code. In his defense, he got the horrible hack from gentoo.) I should have prebuilt binaries in my next aboriginal linux release, I'll post about them on the nommu.org list.

We're working on it. We want this all smoothed out by ELC Europe in october because we're giving our talk there again _and_ we're doing a tutorial where we give away a coupld dozen numato boards and walk everybody through building and installing bitstreams on their own linux laptop, and we'd really like that not to be the _first_ time somebody other than us makes it all work. (We _want_ to focus on teaching people VHDL programming, but there's so much surrounding material that all has to work for that to be useful...)

Oh, linux laptop is good because the Numato boards only wired up 2 pins for their serial port (no data terminal ready, no hardware flow control), so you have to do something like "stty clocal -crtscts -cdtrdsr /dev/ttyUSB0" to see terminal output, and for some reason it's impossible to do this on macosx? Their stty man page says you can do it, but it doesn't work. Possibly something to do with the way numato implemented their USB serial packatization is tickling macosx the wrong way? Works on windows, works on linux, not on mac. We've got a bug report in with numato and I'm told there's progress on that front...

Sorry. Working on it. Have some kernel patches.

Rob

#1 lore raw

PATCH 1/2 New files for 0PF FPGA board.

New files for Open Processor Foundation j2 (superh sh2 compatible open hardware) FPGA board, with enough drivers to boot initramfs to a shell prompt on serial console. See http://0pf.org for details.

arch/sh/boards/board-0pf.c new file +270 -0
@@ -0,0 +1,270 @@
+/*
+ * board-0pf.c
+ *
+ * Copyright (C) 2006 Yoshinori Sato
+ * Copyright (C) 2009 D. Jeff Dionne
+ *
+ * 0PF j-series CPU on FPGA
+ */
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/interrupt.h>
+#include <linux/profile.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/rtc.h>
+#include <asm/machvec.h>
+#include <asm/board-0pf.h>
+
+int shj_irq_demux(int irq)
+{
+	return irq;		/* punt.. */
+}
+
+static void shj_ack_noop(struct irq_data *data)
+{
+	asm("nop;nop");
+	/* Dummy function.  */
+}
+
+static inline void shj_enable_irq(struct irq_data *data)
+{
+	unsigned int irq = data->irq;
+	volatile unsigned int vui;
+
+//	printk("%s: IRQ %d (0x%x)\n", __func__, irq, irq);
+
+	switch (irq) {
+	case PIT_IRQ:
+		//AQ_PIO = 0x0BB;
+		/* enable, lvl 2, vector 64 */
+		AQ_SYS = (1 << 26) |	/* enable PIT */
+		    (0x02 << 20) |	/* interrupt level 2 */
+		    (PIT_IRQ << 12) |	/* vector 64 */
+		    1;		/* turn off interval timer */
+		break;
+
+	case Irq_UART0:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_UART0, 0xf);	/* clear old setting */
+		vui |= ID2Pri(EIrqID_UART0, 0x7);	/* set interrupt level */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_UART1:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_UART1, 0xf);	/* clear old setting */
+		vui |= ID2Pri(EIrqID_UART1, 0x7);	/* set interrupt level */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_GPS:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_GPS, 0xf);	/* clear old setting */
+		vui |= ID2Pri(EIrqID_GPS, 0x7);	/* set interrupt level */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_I2C:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_I2C, 0xf);	/* clear old setting */
+		vui |= ID2Pri(EIrqID_I2C, 0x7);	/* set interrupt level */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_EMAC:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_EMAC, 0xf);	/* clear old setting */
+		vui |= ID2Pri(EIrqID_EMAC, 0x8);	/* set interrupt level */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		printk("EMAC prio is: %x\n", vui);
+		break;
+
+        case Irq_GPIO:
+                vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+                vui &= ~ID2Pri(EIrqID_GPIO, 0xf);       /* clear old setting */
+                vui |= ID2Pri(EIrqID_GPIO, 0x7);        /* set interrupt level */
+                *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+                break;
+
+        case Irq_1PPS: // prio is higher for 1PPS porposes
+                vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+                vui &= ~ID2Pri(EIrqID_1PPS, 0xf);       /* clear old setting */
+                vui |= ID2Pri(EIrqID_1PPS, 0x9);        /* set interrupt level */
+                *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+                printk("1PPS prio is: %x\n", vui);
+                break;
+
+	default:
+		break;
+
+	}
+}
+
+static inline void shj_disable_irq(struct irq_data *data)
+{
+	volatile unsigned int vui;
+	unsigned int irq = data->irq;
+
+	printk("%s: IRQ %d\n", __func__, irq);
+
+	switch (irq) {
+	case PIT_IRQ:
+		/* enable, lvl 2, vector 64 */
+		AQ_SYS = (0 << 26) |	/* disable PIT */
+		    (0x02 << 20) |	/* interrupt level 2 */
+		    (PIT_IRQ << 12) |	/* vector 64 */
+		    1;		/* turn off interval timer */
+		break;
+
+	case Irq_UART0:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_UART0, 0xf);	/* clear setting */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_UART1:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_UART1, 0xf);	/* clear setting */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_GPS:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_GPS, 0xf);	/* clear setting */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_I2C:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_I2C, 0xf);	/* clear setting */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+	case Irq_EMAC:
+		vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+		vui &= ~ID2Pri(EIrqID_EMAC, 0xf);	/* clear setting */
+		*(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+		break;
+
+        case Irq_GPIO:
+                vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+                vui &= ~ID2Pri(EIrqID_GPIO, 0xf);       /* clear setting */
+                *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+                break;
+
+        case Irq_1PPS:
+                vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
+                vui &= ~ID2Pri(EIrqID_1PPS, 0xf);       /* clear setting */
+                *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
+                break;
+
+	default:
+		break;
+	}
+}
+
+static struct irq_chip shj_irq_chip = {
+	.name = "0PF_INTC",
+	.irq_enable = shj_enable_irq,
+	.irq_disable = shj_disable_irq,
+	.irq_ack = shj_ack_noop,
+};
+
+static void __init shj_irq_init(void)
+{
+	int c;
+
+	printk(KERN_INFO "0PF FPGA interrupt controller...\n");
+
+	for (c = 0; c < NR_IRQS; c++) {
+		//irq_desc[c].action = NULL;
+		//irq_desc[c].depth = 1;
+		irq_set_chip_and_handler_name(c, &shj_irq_chip,
+					      handle_simple_irq, "simple");
+	}
+}
+
+#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
+// Commit 7b1f62076 switched this to a pointer
+/*
+ * Should return nanoseconds since last timer tick
+ */
+u32 shj_gettimeoffset(void)
+{
+	u32 clocks_counter = readl(SHJ_PIT_PCNTR);
+
+	return clocks_counter * readl(SHJ_NSEC_PER_CLOCK);
+}
+
+static void __init shj_board_setup(char **cmdline)
+{
+	arch_gettimeoffset = shj_gettimeoffset;
+}
+#else
+#define shj_gettimeoffset 0
+#endif
+
+static struct sh_machine_vector mv_se __initmv = {
+	.mv_name = "0PF_FPGA",
+	//.mv_nr_irqs = 256,
+	.mv_irq_demux = shj_irq_demux,
+	.mv_init_irq = shj_irq_init,
+	.mv_setup = shj_board_setup,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+	// AQ_PIO = 0x011; // GREEN
+
+	if (current->pid)
+		profile_tick(CPU_PROFILING);
+
+	xtime_update(1);
+	update_process_times(user_mode(get_irq_regs()));
+
+	return IRQ_HANDLED;
+}
+
+static void __init start_pit(void)
+{
+	if (request_irq
+	    (PIT_IRQ, timer_interrupt, IRQF_TIMER, "pit", NULL))
+		printk("irq_desc[%p] : fail to register\n", &irq_desc[PIT_IRQ]);
+
+	irq_set_chip_and_handler_name(PIT_IRQ, &shj_irq_chip, handle_edge_irq,
+				      "pit");
+}
+
+static int __init shj_initialise(void)
+{
+	struct irq_data *data;
+
+	pr_info("0PF Machine setup...\n");
+
+	start_pit();
+
+	data = irq_get_irq_data(Irq_UART0);
+	shj_enable_irq(data);
+
+	data = irq_get_irq_data(Irq_UART1);
+	shj_enable_irq(data);
+
+	data = irq_get_irq_data(Irq_EMAC);
+	shj_enable_irq(data);
+
+	data = irq_get_irq_data(PIT_IRQ);
+	shj_enable_irq(data);
+
+	pr_info("0PF Machine setup done.\n");
+
+	return 0;
+}
+
+arch_initcall(shj_initialise);
arch/sh/include/asm/board-0pf.h new file +247 -0

247 lines not on this page · raw message

arch/sh/kernel/cpu/sh2/clock-0pf.c new file +80 -0

80 lines not on this page · raw message

arch/sh/kernel/cpu/sh2/setup-0pf.c new file +82 -0

82 lines not on this page · raw message

arch/sh/configs/0pf_defconfig new file +945 -0

945 lines not on this page · raw message

#2 lore raw

Re: [PATCH 1/2] New files for 0PF FPGA board.

Hi Rob,

Quoted 3 lines · Rob Landley

New files for Open Processor Foundation j2 (superh sh2 compatible open hardware) FPGA board, with enough drivers to boot initramfs to a shell prompt on serial console. See http://0pf.org for details.

Thanks for your patch!

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 11 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +6 -0
@@ -0,0 +1,270 @@
 
+static inline void shj_enable_irq(struct irq_data *data)
+{
+       unsigned int irq = data->irq;
+       volatile unsigned int vui;
+
+//     printk("%s: IRQ %d (0x%x)\n", __func__, irq, irq);

Please no C++ style comments, nor commented-out code.

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 7 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +7 -0
+       switch (irq) {
+       case PIT_IRQ:
+               //AQ_PIO = 0x0BB;
+               /* enable, lvl 2, vector 64 */
+               AQ_SYS = (1 << 26) |    /* enable PIT */
+                   (0x02 << 20) |      /* interrupt level 2 */
+                   (PIT_IRQ << 12) |   /* vector 64 */

Magic numbers need #defines.

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 5 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +5 -0
+                   1;          /* turn off interval timer */
+               break;
+
+       case Irq_UART0:
+               vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);

volatile considered harmful, writel()? (more below)

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 3 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +3 -0
+static void __init shj_irq_init(void)
+{
+       int c;

unsigned int

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 2 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +2 -0
+
+       printk(KERN_INFO "0PF FPGA interrupt controller...\n");

pr_info()

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 11 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +11 -0
+
+       for (c = 0; c < NR_IRQS; c++) {
+               //irq_desc[c].action = NULL;
+               //irq_desc[c].depth = 1;
+               irq_set_chip_and_handler_name(c, &shj_irq_chip,
+                                             handle_simple_irq, "simple");
+       }
+}
+
+#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
+// Commit 7b1f62076 switched this to a pointer

Please don't refer to git commits in comments.

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 3 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +3 -0
+static struct sh_machine_vector mv_se __initmv = {
+       .mv_name = "0PF_FPGA",
+       //.mv_nr_irqs = 256,

No commented-out code/data

arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 5 lines
arch/sh/boards/board-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +5 -0
+static void __init start_pit(void)
+{
+       if (request_irq
+           (PIT_IRQ, timer_interrupt, IRQF_TIMER, "pit", NULL))
+               printk("irq_desc[%p] : fail to register\n", &irq_desc[PIT_IRQ]);

pr_err()

arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 line 2

Quoted 5 lines
arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +2 -0
@@ -0,0 +1,247 @@
+#ifndef SGM_BOARD_H
+#define SGM_BOARD_H

Strange include guard name, not matching file name.

arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 line 3

Quoted 1 line
arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +1 -0
+#define sys_IntTable (*(unsigned*)0x0)

NULL? Besides, it seems unused?

arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 line 4

Quoted 1 line
arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +1 -0
+#define SIC_ENMI       ((unsigned int) 0x1<<31)        /* Emulate NMI */

"BIT(31)" (more below)

arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 line 5

Quoted 1 line
arch/sh/include/asm/board-0pf.h 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +1 -0
+#if 0

No #ifdef'ed-out definitions please

arch/sh/kernel/cpu/sh2/clock-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 9 lines
arch/sh/kernel/cpu/sh2/clock-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +5 -0
@@ -0,0 +1,80 @@
 
+int __init arch_clk_init()
+{
+       int ret;
+
+       printk("%s(): 0PF Clock init...\n", __func__);

pr_debug()?

Quoted 11 lines
arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +7 -0
@@ -0,0 +1,82 @@
 
+#if defined(CONFIG_SERIAL_UARTLITE_0PF)
+static struct resource shj_uartlite_resources[] = {
+       [0] = DEFINE_RES_MEM(0xABCD0100, 16),
+       [1] = DEFINE_RES_IRQ(0x12),
+
+       [2] = DEFINE_RES_MEM(0xABCD0300, 16),
+       [3] = DEFINE_RES_IRQ(0x17),

arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 10 lines
arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +10 -0
+
+       [4] = DEFINE_RES_MEM(0xABCD0400, 16),
+       [5] = DEFINE_RES_IRQ(0x13),
+};
+
+static struct platform_device shj_uartlite_device[] = {
+       [0] = { .name = "uartlite", .id = 0 },
+       [1] = { .name = "uartlite", .id = 1 },
+       [2] = { .name = "uartlite", .id = 2 },
+};

Typically we have only the driver depend on CONFIG_XXX, not the platform code that creates the platform device.

arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 7 lines
arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +7 -0
+#endif
+
+/*****************************************************************************
+ *  0PF FPGA platform devices
+ ****************************************************************************/
+static struct platform_device *shj_devices[] __initdata = {
+#if defined(CONFIG_SERIAL_UARTLITE_0PF)

Idem ditto

arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500

Quoted 12 lines
arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +12 -0
+       shj_uartlite_device,
+       shj_uartlite_device + 1,
+       shj_uartlite_device + 2,
+#endif
+};
+
+static int __init shj_devices_setup(void)
+{
+       int i;
+       pr_info("%s(): registering device resources\n", __func__);
+
+#if defined(CONFIG_SERIAL_UARTLITE_0PF)

idem ditto

arch/sh/configs/0pf_defconfig 2015-06-17 21:47:46.869366542 -0500

Quoted 18 lines
arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-06-17 21:20:05.825356382 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +14 -0
+       for (i = 0; i < ARRAY_SIZE(shj_uartlite_device); i++) {
+               printk("Register UARTLITE resources %d\n", i);
+               if (platform_device_add_resources(
+                               shj_uartlite_device + i,
+                               shj_uartlite_resources + 2 * i,
+                               2))
+                       pr_err("Failed to set uartlite %d IRQ and MEM\n", i);
+
+       }
+#endif
+       platform_add_devices(shj_devices, ARRAY_SIZE(shj_devices));
+
+       return 0;
+}
arch/sh/configs/0pf_defconfig 2015-06-17 21:47:46.869366542 -0500 renamed from dev/null 2015-06-06 04:15:40.702718005 -0500 +0 -0
@@ -0,0 +1,945 @@

I may be mistaken, but this doesn't look like a minimal defconfig as created by "make savedefconfig".

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#3 lore raw

PATCH 2/2 Changes to existing files for 0PF FPGA board.

In reply to Rob Landley

Changes to existing files to add 0pf j2 board support.

arch/sh/Kconfig +16 -1
index 50057fe..c121a92 100644
@@ -66,7 +66,7 @@ config SUPERH32
 	select HAVE_MIXED_BREAKPOINTS_REGS
 	select PERF_EVENTS
 	select ARCH_HIBERNATION_POSSIBLE if MMU
-	select SPARSE_IRQ
+	select SPARSE_IRQ if !CPU_SUBTYPE_0PF
 	select HAVE_CC_STACKPROTECTOR
 
 config SUPERH64
@@ -108,6 +108,9 @@ config ARCH_SUSPEND_POSSIBLE
 config ARCH_HIBERNATION_POSSIBLE
 	def_bool n
 
+config ARCH_USES_GETTIMEOFFSET
+	def_bool n
+
 config SYS_SUPPORTS_APM_EMULATION
 	bool
 	select ARCH_SUSPEND_POSSIBLE
@@ -184,6 +187,11 @@ config CPU_SH2A
 	select CPU_SH2
 	select UNCACHED_MAPPING
 
+config CPU_SH2J
+	bool
+	select CPU_SH2
+	select ARCH_USES_GETTIMEOFFSET
+
 config CPU_SH3
 	bool
 	select CPU_HAS_INTEVT
@@ -303,6 +311,12 @@ config CPU_SUBTYPE_MXG
 	help
 	  Select MX-G if running on an R8A03022BG part.
 
+# SH-2J Processor Support
+
+config CPU_SUBTYPE_0PF
+	bool "Support 0PF J2 SoftCore"
+	select CPU_SH2J
+
 # SH-3 Processor Support
 
 config CPU_SUBTYPE_SH7705
@@ -753,6 +767,7 @@ config ZERO_PAGE_OFFSET
 				SH_7751_SOLUTION_ENGINE
 	default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
 	default "0x00002000" if PAGE_SIZE_8KB
+	default "0x0003F000" if CPU_SUBTYPE_0PF
 	default "0x00001000"
 	help
 	  This sets the default offset of zero page.
arch/sh/Makefile +5 -0
index bf5b3f5..e609157 100644
@@ -4,6 +4,7 @@
 # Copyright (C) 1999  Kaz Kojima
 # Copyright (C) 2002 - 2008  Paul Mundt
 # Copyright (C) 2002  M. R. Brown
+# Copyright (C) 2012  SEI, Inc. (sh2j)
 #
 # This file is subject to the terms and conditions of the GNU General Public
 # License.  See the file "COPYING" in the main directory of this archive
@@ -19,6 +20,7 @@ isa-y					:= any
 isa-$(CONFIG_SH_DSP)			:= sh
 isa-$(CONFIG_CPU_SH2)			:= sh2
 isa-$(CONFIG_CPU_SH2A)			:= sh2a
+isa-$(CONFIG_CPU_SH2J)			:= sh2j
 isa-$(CONFIG_CPU_SH3)			:= sh3
 isa-$(CONFIG_CPU_SH4)			:= sh4
 isa-$(CONFIG_CPU_SH4A)			:= sh4a
@@ -31,6 +33,7 @@ isa-y					:= $(isa-y)-up
 endif
 
 cflags-$(CONFIG_CPU_SH2)		:= $(call cc-option,-m2,)
+cflags-$(CONFIG_CPU_SH2J)		:= $(call cc-option,-m2,)
 cflags-$(CONFIG_CPU_SH2A)		+= $(call cc-option,-m2a,) \
 					   $(call cc-option,-m2a-nofpu,) \
 					   $(call cc-option,-m4-nofpu,)
@@ -91,6 +94,7 @@ defaultimage-$(CONFIG_SH_SH7757LCR)		:= uImage
 defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE)	:= uImage
 defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE)	:= vmlinux
 defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE)	:= vmlinux
+defaultimage-$(CONFIG_SH_0PF)			:= vmlinux
 
 # Set some sensible Kbuild defaults
 KBUILD_IMAGE		:= $(defaultimage-y)
@@ -173,6 +177,7 @@ core-$(CONFIG_HD6446X_SERIES)	+= arch/sh/cchips/hd6446x/
 # As an example, in order of preference, SH-2A > SH-2 > common definitions.
 #
 cpuincdir-$(CONFIG_CPU_SH2A)	+= cpu-sh2a
+cpuincdir-$(CONFIG_CPU_SH2J)	+= cpu-sh2j
 cpuincdir-$(CONFIG_CPU_SH2)	+= cpu-sh2
 cpuincdir-$(CONFIG_CPU_SH3)	+= cpu-sh3
 cpuincdir-$(CONFIG_CPU_SH4A)	+= cpu-sh4a
arch/sh/boards/Kconfig +7 -0
index 89963d13..c6721d2 100644
@@ -90,6 +90,13 @@ config SH_7343_SOLUTION_ENGINE
 	  Select 7343 SolutionEngine if configuring for a Hitachi
 	  SH7343 (SH-Mobile 3AS) evaluation board.
 
+config 0PF_FPGA
+	bool "0PF FPGA"
+	depends on CPU_SUBTYPE_0PF
+	help
+	  Select 0PF_FPGA if you are configuring for an FPGA with
+	  the SH2j-workalike SoftCore from http://0pf.org
+
 config SH_HP6XX
 	bool "HP6XX"
 	select SYS_SUPPORTS_APM_EMULATION
arch/sh/boards/Makefile +1 -0
index 975a0f6..51a7eb3 100644
@@ -15,3 +15,4 @@ obj-$(CONFIG_SH_TITAN)		+= board-titan.o
 obj-$(CONFIG_SH_SH7757LCR)	+= board-sh7757lcr.o
 obj-$(CONFIG_SH_APSH4A3A)	+= board-apsh4a3a.o
 obj-$(CONFIG_SH_APSH4AD0A)	+= board-apsh4ad0a.o
+obj-$(CONFIG_0PF_FPGA)		+= board-0pf.o
arch/sh/include/asm/processor.h +1 -1
index 1506897..aedabf2 100644
@@ -15,7 +15,7 @@
  */
 enum cpu_type {
 	/* SH-2 types */
-	CPU_SH7619,
+	CPU_SH7619, CPU_0PF,
 
 	/* SH-2A types */
 	CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
arch/sh/include/cpu-sh2/cpu/cache.h +4 -0
index aa1b2b9..1da5abb 100644
@@ -38,6 +38,10 @@
 #define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
 #define CACHE_PHYSADDR_MASK	0x1ffffc00
 
+#elif defined(CONFIG_CPU_SUBTYPE_0PF)
+#define CCR			0xabcd00c0
+#define CCR_CACHE_ENABLE	0x80000000
+#define CCR_CACHE_RESET		0x101
 #endif
 
 #endif /* __ASM_CPU_SH2_CACHE_H */
arch/sh/kernel/cpu/init.c +1 -1
index 0d7360d..cda35ce 100644
@@ -106,7 +106,7 @@ void __attribute__ ((weak)) l2_cache_init(void)
 /*
  * Generic first-level cache init
  */
-#ifdef CONFIG_SUPERH32
+#if defined(CONFIG_SUPERH32) && !defined(CONFIG_CPU_SUBTYPE_0PF)
 static void cache_init(void)
 {
 	unsigned long ccr, flags;
arch/sh/kernel/cpu/proc.c +1 -0
index 9e6624c..4381fc2 100644
@@ -26,6 +26,7 @@ static const char *cpu_name[] = {
 	[CPU_SH5_101]	= "SH5-101",	[CPU_SH5_103]	= "SH5-103",
 	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",
 	[CPU_SH7366]	= "SH7366",	[CPU_SH7724]	= "SH7724",
+	[CPU_0PF]	= "SH2J-0PF",
 	[CPU_SH7372]	= "SH7372",	[CPU_SH7734]	= "SH7734",
 	[CPU_SH_NONE]	= "Unknown"
 };
arch/sh/kernel/cpu/sh2/Makefile +1 -0
index f0f059a..7502611 100644
@@ -5,3 +5,4 @@
 obj-y	:= ex.o probe.o entry.o
 
 obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o clock-sh7619.o
+obj-$(CONFIG_CPU_SUBTYPE_0PF) += setup-0pf.o clock-0pf.o
arch/sh/kernel/cpu/sh2/entry.S +19 -1
index c8a4331..3c997c9 100644
@@ -3,6 +3,7 @@
  *
  * The SH-2 exception entry
  *
+ * Copyright (C) 2012  SEI,Inc.
  * Copyright (C) 2005-2008 Yoshinori Sato
  * Copyright (C) 2005  AXE,Inc.
  *
@@ -147,7 +148,11 @@ ENTRY(exception_handler)
 	mov	#32,r8
 	cmp/hs	r8,r9
 	bt	trap_entry	! 64 > vec >= 32  is trap
-
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+	mov	#16,r8
+	cmp/hs	r8,r9
+	bt	interrupt_entry	! 32 > vec >= 16  is interrupt
+#endif
 	mov.l	4f,r8
 	mov	r9,r4
 	shll2	r9
@@ -245,6 +250,19 @@ ENTRY(address_error_trap_handler)
 	.align	2
 1:	.long	do_address_error
 
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+ENTRY(pc_address_error_trap_handler)
+	mov	r15,r4				! regs
+	mov	#OFF_PC,r0
+	mov.l	@(r0,r15),r6			! pc
+	mov.l	1f,r0
+	jmp	@r0
+	 mov	#0,r5				! writeaccess is unknown
+
+	.align	2
+1:	.long	do_pc_address_error
+#endif // CONFIG_CPU_SUBTYPE_0PF
+
 restore_all:
 	stc	sr,r0
 	or	#0xf0,r0
arch/sh/kernel/cpu/sh2/probe.c +6 -0
index 6c687ae..9c9e401 100644
@@ -24,6 +24,12 @@ void cpu_probe(void)
 	boot_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
 	boot_cpu_data.dcache.flags		= 0;
 #endif
+
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+	boot_cpu_data.type                      = CPU_0PF;
+	boot_cpu_data.dcache.flags              = 0;
+#endif
+
 	/*
 	 * SH-2 doesn't have separate caches
 	 */
arch/sh/kernel/irq.c +17 -2
index eb10ff8..7de9bcb 100644
@@ -20,6 +20,8 @@
 #include <asm/thread_info.h>
 #include <cpu/mmu_context.h>
 
+#include <asm/board-0pf.h>
+
 atomic_t irq_err_count;
 
 /*
@@ -175,11 +177,24 @@ void do_softirq_own_stack(void)
 	);
 }
 #else
+#define noinline __attribute__((noinline))
+static noinline void handle_irq_UART0(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_UART1(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_GPS(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_EMAC(unsigned int irq) { generic_handle_irq(irq); }
 static inline void handle_one_irq(unsigned int irq)
 {
-	generic_handle_irq(irq);
+	switch(irq) {
+	case Irq_UART0: handle_irq_UART0(irq); break;
+	case Irq_UART1: handle_irq_UART1(irq); break;
+	case Irq_GPS:   handle_irq_GPS(irq); break;
+	case Irq_EMAC:  handle_irq_EMAC(irq); break;
+	default:
+		generic_handle_irq(irq);
+		break;
+	}
 }
-#endif
+#endif // CONFIG_IRQSTACKS
 
 asmlinkage __irq_entry int do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
arch/sh/kernel/traps_32.c +12 -0
index ff63934..cd09376 100644
@@ -34,6 +34,7 @@
 #ifdef CONFIG_CPU_SH2
 # define TRAP_RESERVED_INST	4
 # define TRAP_ILLEGAL_SLOT_INST	6
+# define TRAP_PC_ADDRESS_ERROR	8 // Aug 20, 2012 ulianov - SEI extension - PC governor
 # define TRAP_ADDRESS_ERROR	9
 # ifdef CONFIG_CPU_SH2A
 #  define TRAP_UBC		12
@@ -458,6 +459,14 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 	return ret;
 }
 
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+asmlinkage void do_pc_address_error(struct pt_regs *regs,
+				 unsigned long writeaccess,
+				 unsigned long address)
+{
+}
+#endif // CONFIG_CPU_SUBTYPE_0PF
+
 /*
  * Handle various address error exceptions:
  *  - instruction address error:
@@ -779,6 +788,9 @@ void __init trap_init(void)
 #endif
 
 #ifdef CONFIG_CPU_SH2
+    #if defined(CONFIG_CPU_SUBTYPE_0PF)
+	set_exception_table_vec(TRAP_PC_ADDRESS_ERROR, address_error_trap_handler);
+    #endif
 	set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 #endif
 #ifdef CONFIG_CPU_SH2A
arch/sh/mm/cache-sh2.c +26 -0
index a74259f..438eadb 100644
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2002 Paul Mundt
  * Copyright (C) 2008 Yoshinori Sato
+ * Copyright (C) 2012 SEI, Inc.
  *
  * Released under the terms of the GNU GPL v2.0.
  */
@@ -16,6 +17,30 @@
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+
+// Just flush the whole thing each time
+static void j2_flush_icache_range(void *fwoosh)
+{
+	__raw_writel(CCR_CACHE_RESET, CCR);
+}
+
+// This should never happen, but...
+static void j2_flush_icache_page(void *fwoosh)
+{
+	__raw_writel(CCR_CACHE_RESET, CCR);
+}
+
+void __init sh2_cache_init(void)
+{
+	local_flush_icache_range = j2_flush_icache_range;
+	local_flush_icache_page = j2_flush_icache_page;
+	boot_cpu_data.dcache.n_aliases = 0;
+
+	__raw_writel(CCR_CACHE_RESET, CCR);
+}
+
+#else
 static void sh2__flush_wback_region(void *start, int size)
 {
 	unsigned long v;
@@ -89,3 +114,4 @@ void __init sh2_cache_init(void)
 	__flush_purge_region		= sh2__flush_purge_region;
 	__flush_invalidate_region	= sh2__flush_invalidate_region;
 }
+#endif
arch/sh/mm/cache.c +10 -8
index f770e39..17908f7 100644
@@ -258,14 +258,16 @@ static void __init emit_cache_params(void)
 		boot_cpu_data.icache.entry_mask,
 		boot_cpu_data.icache.alias_mask,
 		boot_cpu_data.icache.n_aliases);
-	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-		boot_cpu_data.dcache.ways,
-		boot_cpu_data.dcache.sets,
-		boot_cpu_data.dcache.way_incr);
-	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-		boot_cpu_data.dcache.entry_mask,
-		boot_cpu_data.dcache.alias_mask,
-		boot_cpu_data.dcache.n_aliases);
+	if (boot_cpu_data.dcache.n_aliases) {
+		printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
+			boot_cpu_data.dcache.ways,
+			boot_cpu_data.dcache.sets,
+			boot_cpu_data.dcache.way_incr);
+		printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
+			boot_cpu_data.dcache.entry_mask,
+			boot_cpu_data.dcache.alias_mask,
+			boot_cpu_data.dcache.n_aliases);
+	}
 
 	/*
 	 * Emit Secondary Cache parameters if the CPU has a probed L2.
drivers/tty/serial/Kconfig +7 -1
index f8120c1b..aae8d72 100644
@@ -594,7 +594,7 @@ config SERIAL_IMX_CONSOLE
 
 config SERIAL_UARTLITE
 	tristate "Xilinx uartlite serial port support"
-	depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE || ARCH_ZYNQ
+	depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE || ARCH_ZYNQ || CPU_SUBTYPE_0PF
 	select SERIAL_CORE
 	help
 	  Say Y here if you want to use the Xilinx uartlite serial controller.
@@ -611,6 +611,12 @@ config SERIAL_UARTLITE_CONSOLE
 	  console (the system console is the device which receives all kernel
 	  messages and warnings and which allows logins in single user mode).
 
+config SERIAL_UARTLITE_0PF
+       tristate "Support 0PF UARTLITEs"
+       depends on SERIAL_UARTLITE = y && CPU_SUBTYPE_0PF
+       help
+         Say Y here to set up 0PF's UARTLITEs.
+
 config SERIAL_SUNCORE
 	bool
 	depends on SPARC
#4 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Quoted 2 lines · Rob Landley

Changes to existing files to add 0pf j2 board support.

That's the second worse commit message and subject: line I've read today.

And there's no signed off by line.

And there was no 1/2 patch sent.

And, most importantly:

arch/sh/Kconfig

Quoted 1 line
arch/sh/Kconfig +0 -0

I don't care about arch/sh/ stuff, why are you sending this to me?

You have a bit of work to do here...

greg k-h

#5 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Quoted 6 lines · On Thu, 18 Jun 2015 10:59:31 -0700 Greg Kroah-Hartman…
Quoted 2 lines · Rob Landley

Changes to existing files to add 0pf j2 board support.

That's the second worse commit message and subject: line I've read today.

Only the second worse today? Damn, you must get a lot of crappy change logs.

Quoted 10 lines

And there's no signed off by line.

And there was no 1/2 patch sent.

And, most importantly:

arch/sh/Kconfig

Quoted 1 line
arch/sh/Kconfig +0 -0

I don't care about arch/sh/ stuff, why are you sending this to me?

Because even when you don't care, you still give back constructive feedback ;-)

-- Steve

Quoted 4 lines

You have a bit of work to do here...

greg k-h

author Reviewed-by D. Jeff Dionne
#6 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

In reply to Greg Kroah-Hartman
Quoted 8 lines · Greg Kroah-Hartman
Quoted 2 lines · Rob Landley

Changes to existing files to add 0pf j2 board support.

That's the second worse commit message and subject: line I've read today.

And there's no signed off by line.

My bad. I've always sucked at filling out paperwork, and I didn't expect this to go in as is. But for the sake of following the official procedures (well, step 11 of of SubmittingPatches, it's not mentioned in any of the 26 steps of SubmitChecklist), here's the requested certification:

Quoted 1 line

And there was no 1/2 patch sent.

I sent one, which made it to the archive...

http://lkml.iu.edu/hypermail/linux/kernel/1506.2/02539.html

Quoted 5 lines

And, most importantly:

arch/sh/Kconfig

Quoted 1 line
arch/sh/Kconfig +0 -0

I don't care about arch/sh/ stuff, why are you sending this to me?

$ scripts/get_maintainer.pl j2-oldfiles.patch | grep Greg
Greg Kroah-Hartman <[email protected]> (maintainer:SERIAL DRIVERS)

Sorry, my bad, I was trying to follow the documented procedure. Personally I'd have trimmed the cc: list but filling things out in triplicate seems to be all the rage these days.

Quoted 1 line

You have a bit of work to do here...

As I mentioned in 0/2, yes. But "release early, release often" and all that.

(Or did we stop doing that now the Linux Foundation's in charge? I'm still stuck in the hobbyist era from back before we had a foundation with committees and a hierarchy where you need to go through proper channels and three dozen patch submission steps in two different files and all that. I'm trying to keep up, but I've always been really bad at bureaucracy...)

Quoted 2 lines

greg k-h
.

Rob
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in

#7 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Quoted 10 lines · Rob Landley
Quoted 8 lines · Greg Kroah-Hartman
Quoted 2 lines · Rob Landley

Changes to existing files to add 0pf j2 board support.

That's the second worse commit message and subject: line I've read today.

And there's no signed off by line.

Quoted 7 lines

My bad. I've always sucked at filling out paperwork, and I didn't expect this to go in as is. But for the sake of following the official procedures (well, step 11 of of SubmittingPatches, it's not mentioned in any of the 26 steps of SubmitChecklist), here's the requested certification:

You didn't do the 26 steps of SubmitChecklist, as step 5 would have caught almost all of these issues.

Quoted 5 lines
Quoted 1 line

And there was no 1/2 patch sent.

I sent one, which made it to the archive...

http://lkml.iu.edu/hypermail/linux/kernel/1506.2/02539.html

But you didn't cc: me on that, how am I supposed to know?

Quoted 6 lines
Quoted 5 lines

And, most importantly:

arch/sh/Kconfig

Quoted 1 line
arch/sh/Kconfig +0 -0

I don't care about arch/sh/ stuff, why are you sending this to me?

Quoted 6 lines
$ scripts/get_maintainer.pl j2-oldfiles.patch | grep Greg
Greg Kroah-Hartman <[email protected]> (maintainer:SERIAL DRIVERS)

Sorry, my bad, I was trying to follow the documented procedure. Personally I'd have trimmed the cc: list but filling things out in triplicate seems to be all the rage these days.

No, you need to break your patch up properly, a single patch hitting all of these files has never been ok.

Quoted 5 lines
Quoted 1 line

You have a bit of work to do here...

As I mentioned in 0/2, yes. But "release early, release often" and all that.

(Or did we stop doing that now the Linux Foundation's in charge?

Seriously? It's one thing to cc: a ton of people with a patch that for 90% of it, isn't relevant to them, and isn't even something they can do anything with. It's another thing to rant against those who try to point out how to solve your issues.

Quoted 5 lines

I'm still stuck in the hobbyist era from back before we had a foundation with committees and a hierarchy where you need to go through proper channels and three dozen patch submission steps in two different files and all that. I'm trying to keep up, but I've always been really bad at bureaucracy...)

There is no such thing here, you know better than that, stop trying to troll, it's not very becoming.

greg k-h

#8 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Quoted 16 lines · Greg Kroah-Hartman
Quoted 15 lines · Rob Landley
Quoted 8 lines · Greg Kroah-Hartman
Quoted 2 lines · Rob Landley

Changes to existing files to add 0pf j2 board support.

That's the second worse commit message and subject: line I've read today.

And there's no signed off by line.

My bad. I've always sucked at filling out paperwork, and I didn't expect this to go in as is. But for the sake of following the official procedures (well, step 11 of of SubmittingPatches, it's not mentioned in any of the 26 steps of SubmitChecklist), here's the requested certification:

Quoted 5 lines
Quoted 2 lines

You didn't do the 26 steps of SubmitChecklist, as step 5 would have caught almost all of these issues.

I did not, yes. That's what I was saying above.

(Sorry, probably should have stuck [RFC] on this. I mentioned in the 0/ message that it had several large known todo items. The consensus is I should do device tree conversion before resubmitting, so working on that.)

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

And there was no 1/2 patch sent.

I sent one, which made it to the archive...

http://lkml.iu.edu/hypermail/linux/kernel/1506.2/02539.html

But you didn't cc: me on that, how am I supposed to know?

Ah, I didn't consistently cc: enough people. Got it.

Quoted 9 lines
Quoted 9 lines
Quoted 5 lines

And, most importantly:

arch/sh/Kconfig

Quoted 1 line
arch/sh/Kconfig +0 -0

I don't care about arch/sh/ stuff, why are you sending this to me?

$ scripts/get_maintainer.pl j2-oldfiles.patch | grep Greg
Greg Kroah-Hartman <[email protected]> (maintainer:SERIAL DRIVERS)
Quoted 6 lines
Quoted 3 lines

Sorry, my bad, I was trying to follow the documented procedure. Personally I'd have trimmed the cc: list but filling things out in triplicate seems to be all the rage these days.

No, you need to break your patch up properly, a single patch hitting all of these files has never been ok.

So I've been told, yes.

Quoted 9 lines
Quoted 5 lines
Quoted 1 line

You have a bit of work to do here...

As I mentioned in 0/2, yes. But "release early, release often" and all that.

(Or did we stop doing that now the Linux Foundation's in charge?

Seriously? It's one thing to cc: a ton of people with a patch that for 90% of it, isn't relevant to them, and isn't even something they can do anything with.

Ah, I cc:'d too many people. Got it. (Trimming cc: list.)

I'm still getting cc'd on Documentation/ patches, despite bowing out of messing with that in 2013 and not really doing _any_ kernel stuff in over a year. Didn't realize it was a thing I should be avoiding.

Quoted 2 lines

It's another thing to rant against those who try to point out how to solve your issues.

[Way too long a reply to this bit deleted.]

Let's just say there are a number of historical reasons I've addressed you as "my nemesis" when we bumped into each other at conferences over the past few years.

At this point I start my replies to you with a level of exasperation that's probably not helpful. I'll try to compensate.

Quoted 7 lines
Quoted 5 lines

I'm still stuck in the hobbyist era from back before we had a foundation with committees and a hierarchy where you need to go through proper channels and three dozen patch submission steps in two different files and all that. I'm trying to keep up, but I've always been really bad at bureaucracy...)

There is no such thing here, you know better than that,

We're discussing my failure to correctly follow a 26 step procedure followed by a second 15 step procedure. Your first objection was that I didn't sign the right line to provide a mandatory certification resulting from historical legal action.

You're enforcing these procedures from an executive position within a hierarchy (tier 3 of 4 in developer/maintainer/subsystem/architect review cycle, if you approve requests you submit them up the chain for further approval), on behalf of a foundation that describes itself as a "consortium" and links to an antitrust policy (and three other policies) from every page of its website, which got its name during a merger with a standards body a decade ago.

No such thing as bureaucracy here. Got it.

Quoted 1 line

stop trying to troll, it's not very becoming.

I wasn't saying bureaucracy is a bad thing, just that I'm bad at it.

Trying to coordinate ten thousand people on six continents working on a quarter-century old project with a globetrotting annual meeting that's closed to the public isn't the same as emailing a college student in his bedroom about the thing he started over the summer that a couple dozen other people liked. I'm aware of this.

Quoted 1 line

greg k-h

Rob

#9 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

In reply to Rob Landley

Hi Rob,

Quoted 1 line · Rob Landley

Changes to existing files to add 0pf j2 board support.

Thanks for your patch!

Like Greg already said, splitting it up in logical parts and providing useful patch descriptions would be highly appreciated.

arch/sh/Makefile isa-y := $(isa-y)-up · line 36

Quoted 10 lines
arch/sh/Makefile +1 -0
index bf5b3f5..e609157 100644
@@ -31,6 +33,7 @@ isa-y                                 := $(isa-y)-up
 endif
 
 cflags-$(CONFIG_CPU_SH2)               := $(call cc-option,-m2,)
+cflags-$(CONFIG_CPU_SH2J)              := $(call cc-option,-m2,)

This is superfluous, as CPU_SH2J selects CPU_SH2.

arch/sh/kernel/irq.c line 23

Quoted 9 lines
arch/sh/kernel/irq.c +1 -0
index eb10ff8..7de9bcb 100644
@@ -20,6 +20,8 @@
 #include <asm/thread_info.h>
 #include <cpu/mmu_context.h>
 
+#include <asm/board-0pf.h>

Board-specific inclusion in generic sh source file?

Quoted 15 lines
arch/sh/kernel/irq.c +6 -0
+
 atomic_t irq_err_count;
 
 /*
@@ -175,11 +177,24 @@ void do_softirq_own_stack(void)
        );
 }
 #else
+#define noinline __attribute__((noinline))
+static noinline void handle_irq_UART0(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_UART1(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_GPS(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_EMAC(unsigned int irq) { generic_handle_irq(irq); }
 static inline void handle_one_irq(unsigned int irq)
 {

arch/sh/kernel/irq.c void do_softirq_own_stack(void) · line 195

Quoted 10 lines
arch/sh/kernel/irq.c +9 -1
-       generic_handle_irq(irq);
+       switch(irq) {
+       case Irq_UART0: handle_irq_UART0(irq); break;
+       case Irq_UART1: handle_irq_UART1(irq); break;
+       case Irq_GPS:   handle_irq_GPS(irq); break;
+       case Irq_EMAC:  handle_irq_EMAC(irq); break;
+       default:
+               generic_handle_irq(irq);
+               break;
+       }

What's the purpose of this change?

arch/sh/kernel/irq.c void do_softirq_own_stack(void) · line 197

Quoted 3 lines
arch/sh/kernel/irq.c +1 -1
 }
-#endif
+#endif // CONFIG_IRQSTACKS

Please no C++-style comments (scripts/checkpatch.pl?)

arch/sh/mm/cache-sh2.c line 22

Quoted 12 lines
arch/sh/mm/cache-sh2.c +3 -0
index a74259f..438eadb 100644
@@ -16,6 +17,30 @@
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 
+#if defined(CONFIG_CPU_SUBTYPE_0PF)
+
+// Just flush the whole thing each time

Likewise

arch/sh/mm/cache-sh2.c line 28

Quoted 6 lines
arch/sh/mm/cache-sh2.c +6 -0
+static void j2_flush_icache_range(void *fwoosh)
+{
+       __raw_writel(CCR_CACHE_RESET, CCR);
+}
+
+// This should never happen, but...

Likewise.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#10 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

[Trimmed greg at what I'm interpreting as his request.]

Quoted 9 lines · Geert Uytterhoeven

Hi Rob,

Quoted 1 line · Rob Landley

Changes to existing files to add 0pf j2 board support.

Thanks for your patch!

Like Greg already said, splitting it up in logical parts and providing useful patch descriptions would be highly appreciated.

I actually don't know how to split it up further. The initial port was done by a series of contractors (in Russia, I think), and then I inherited it to try to get something releasable. This is the smallest chunk I could get to actually boot.

I suppose I could send you the serial driver by itself, and _then_ the board, but it wouldn't compile if nothing uses it. (Similarly you can't boot the board without a serial console...)

Quoted 5 lines
Quoted 4 lines
arch/sh/Makefile +0 -0
index bf5b3f5..e609157 100644
Quoted 7 lines

arch/sh/Makefile isa-y := $(isa-y)-up · line 36

Quoted 5 lines
arch/sh/Makefile +1 -0
@@ -31,6 +33,7 @@ isa-y                                 := $(isa-y)-up
 endif
 
 cflags-$(CONFIG_CPU_SH2)               := $(call cc-option,-m2,)
+cflags-$(CONFIG_CPU_SH2J)              := $(call cc-option,-m2,)

This is superfluous, as CPU_SH2J selects CPU_SH2.

Ooh, thanks.

Quoted 11 lines

arch/sh/kernel/irq.c line 23

Quoted 9 lines
arch/sh/kernel/irq.c +1 -0
index eb10ff8..7de9bcb 100644
@@ -20,6 +20,8 @@
 #include <asm/thread_info.h>
 #include <cpu/mmu_context.h>
 
+#include <asm/board-0pf.h>

Board-specific inclusion in generic sh source file?

Gah, I thought I'd whacked all of those. (Staring at it too long to see some of this stuff anymore...)

Quoted 19 lines
Quoted 19 lines
arch/sh/kernel/irq.c +9 -1
+
 atomic_t irq_err_count;
 
 /*
@@ -175,11 +177,24 @@ void do_softirq_own_stack(void)
        );
 }
 #else
+#define noinline __attribute__((noinline))
+static noinline void handle_irq_UART0(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_UART1(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_GPS(unsigned int irq) { generic_handle_irq(irq); }
+static noinline void handle_irq_EMAC(unsigned int irq) { generic_handle_irq(irq); }
 static inline void handle_one_irq(unsigned int irq)
 {
-       generic_handle_irq(irq);
+       switch(irq) {
+       case Irq_UART0: handle_irq_UART0(irq); break;
+       case Irq_UART1: handle_irq_UART1(irq); break;
Quoted 8 lines

arch/sh/kernel/irq.c void do_softirq_own_stack(void) · line 195

Quoted 6 lines
arch/sh/kernel/irq.c +6 -0
+       case Irq_GPS:   handle_irq_GPS(irq); break;
+       case Irq_EMAC:  handle_irq_EMAC(irq); break;
+       default:
+               generic_handle_irq(irq);
+               break;
+       }

What's the purpose of this change?

Honestly, your guess is as good as mine. (Sorry, I'll move it to a board-specific file. I mentioned needing to redo the interrupt logic _entirely_, it should totally be using SPARSE_IRQ. And in fact most of the above is for drivers I trimmed out of this submission anyway.)

Quoted 5 lines

arch/sh/kernel/irq.c void do_softirq_own_stack(void) · line 197

Quoted 3 lines
arch/sh/kernel/irq.c +1 -1
 }
-#endif
+#endif // CONFIG_IRQSTACKS

Please no C++-style comments (scripts/checkpatch.pl?)

I expect it to try to reach through the screen and throttle me, but sure...

(Now the reason _I_ thought you'd reject it had more to do with not having converted it to device tree yet, and things on that level. But I wanted to get it out there so people outside $DAYJOB can test the hardware. We did a linuxcon japan presentation which lwn.net covered, and we're getting pokes about "where can I download this", so...)

Rob
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#11 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Hi Rob,

Quoted 9 lines · Rob Landley
Quoted 7 lines · Geert Uytterhoeven
Quoted 1 line · Rob Landley

Changes to existing files to add 0pf j2 board support.

Thanks for your patch!

Like Greg already said, splitting it up in logical parts and providing useful patch descriptions would be highly appreciated.

Quoted 8 lines

I actually don't know how to split it up further. The initial port was done by a series of contractors (in Russia, I think), and then I inherited it to try to get something releasable. This is the smallest chunk I could get to actually boot.

I suppose I could send you the serial driver by itself, and _then_ the board, but it wouldn't compile if nothing uses it. (Similarly you can't boot the board without a serial console...)

You don't have to send in a big initial patch that actually boots. For new architecture/SoC/board support, just split it in logical hunks, and submit it in some logical order that always builds.

E.g.:
- SoC core support (arch/sh/),
- Board support (arch/sh/),
- Drivers.

The first two should go in through akpm (sh is orphaned), the rest through the individual subsystem maintainers.

Quoted 2 lines

(Now the reason _I_ thought you'd reject it had more to do with not having converted it to device tree yet, and things on that level. But I

Sh is an existing supported architecture, so DT is not a hard requirement. If you would have waited until after the removal of sh, it would be much harder :-) (cfr. h8300, but Sato-san did a great job there, with DT, CCF, ...)

Quoted 3 lines

wanted to get it out there so people outside $DAYJOB can test the hardware. We did a linuxcon japan presentation which lwn.net covered, and we're getting pokes about "where can I download this", so...)

It's great to hear there's so much interest in this! Let's hope this will attract more actual contributors...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in

#12 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Quoted 25 lines · Geert Uytterhoeven

Hi Rob,

Quoted 9 lines · Rob Landley
Quoted 7 lines · Geert Uytterhoeven
Quoted 1 line · Rob Landley

Changes to existing files to add 0pf j2 board support.

Thanks for your patch!

Like Greg already said, splitting it up in logical parts and providing useful patch descriptions would be highly appreciated.

Quoted 8 lines

I actually don't know how to split it up further. The initial port was done by a series of contractors (in Russia, I think), and then I inherited it to try to get something releasable. This is the smallest chunk I could get to actually boot.

I suppose I could send you the serial driver by itself, and _then_ the board, but it wouldn't compile if nothing uses it. (Similarly you can't boot the board without a serial console...)

You don't have to send in a big initial patch that actually boots. For new architecture/SoC/board support, just split it in logical hunks, and submit it in some logical order that always builds.

Quoted 7 lines

E.g.:
- SoC core support (arch/sh/),
- Board support (arch/sh/),
- Drivers.

The first two should go in through akpm (sh is orphaned), the rest through the individual subsystem maintainers.

I'm aware sh is orphaned
(http://www.openwall.com/lists/musl/2014/02/17/3). I'm trying to do something about that.

I'm not up to maintaining an architecture myself (after the kernel.org/doc thing I walked away from kernel stuff for most of a year, as you can see I'm a bit out of practice), but I spoke to Yoshinori Sato (who used to maintain sh2, and only dropped it when renesas discontinued the hardware) and he said he might be interested in returning as a co-maintainer.

(I note that I've been regression testing and fixing sh4 in my aboriginal linux project for several years now, although it's been quiescent enough on the kernel side the majority of my posts about it seem to be qemu issues, from
https://lists.gnu.org/archive/html/qemu-devel/2010-03/msg00976.html to
http://comments.gmane.org/gmane.comp.emulators.qemu/294066 . Dealing with sh2 is new to me, but it's also my day job these days. :)

Quoted 4 lines
Quoted 2 lines

(Now the reason _I_ thought you'd reject it had more to do with not having converted it to device tree yet, and things on that level. But I

Sh is an existing supported architecture, so DT is not a hard requirement.

Yeah, but new board... And it's the right thing to do.

Quoted 2 lines

If you would have waited until after the removal of sh, it would be much harder :-) (cfr. h8300, but Sato-san did a great job there, with DT, CCF, ...)

Indeed he did. We had lunch with him when I was in Japan a couple weeks ago.

I've got the references I need to do this, just... lots of shoveling on a lot of fronts to do right now. (And I mentioned like 3 other things I already know I need to fix in the 0/2 message.)

Quoted 6 lines
Quoted 3 lines

wanted to get it out there so people outside $DAYJOB can test the hardware. We did a linuxcon japan presentation which lwn.net covered, and we're getting pokes about "where can I download this", so...)

It's great to hear there's so much interest in this! Let's hope this will attract more actual contributors...

The "where can I download this" is now the developer tab of 0pf.org by the way. And the mailing lists are on lists.nommu.org.

I'll try to submit an updated patch set in the next couple days.

Thanks,

Rob
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#13 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

Hi Rob,

Quoted 6 lines · Rob Landley
Quoted 4 lines
Quoted 2 lines

(Now the reason _I_ thought you'd reject it had more to do with not having converted it to device tree yet, and things on that level. But I

Sh is an existing supported architecture, so DT is not a hard requirement.

Yeah, but new board... And it's the right thing to do.

Still, people wouldn't be unhappy if you added DT support ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in

maintainer
#14 lore raw

Re: [PATCH 2/2] Changes to existing files for 0PF FPGA board.

In reply to Rob Landley
Quoted 54 lines · Rob Landley
Quoted 25 lines · Geert Uytterhoeven

Hi Rob,

Quoted 9 lines · Rob Landley
Quoted 7 lines · Geert Uytterhoeven
Quoted 1 line · Rob Landley

Changes to existing files to add 0pf j2 board support.

Thanks for your patch!

Like Greg already said, splitting it up in logical parts and providing useful patch descriptions would be highly appreciated.

Quoted 8 lines

I actually don't know how to split it up further. The initial port was done by a series of contractors (in Russia, I think), and then I inherited it to try to get something releasable. This is the smallest chunk I could get to actually boot.

I suppose I could send you the serial driver by itself, and _then_ the board, but it wouldn't compile if nothing uses it. (Similarly you can't boot the board without a serial console...)

You don't have to send in a big initial patch that actually boots. For new architecture/SoC/board support, just split it in logical hunks, and submit it in some logical order that always builds.

Quoted 7 lines

E.g.:
- SoC core support (arch/sh/),
- Board support (arch/sh/),
- Drivers.

The first two should go in through akpm (sh is orphaned), the rest through the individual subsystem maintainers.

I'm aware sh is orphaned
(http://www.openwall.com/lists/musl/2014/02/17/3). I'm trying to do something about that.

I'm not up to maintaining an architecture myself (after the kernel.org/doc thing I walked away from kernel stuff for most of a year, as you can see I'm a bit out of practice), but I spoke to Yoshinori Sato (who used to maintain sh2, and only dropped it when renesas discontinued the hardware) and he said he might be interested in returning as a co-maintainer.

(I note that I've been regression testing and fixing sh4 in my aboriginal linux project for several years now, although it's been quiescent enough on the kernel side the majority of my posts about it seem to be qemu issues, from
https://lists.gnu.org/archive/html/qemu-devel/2010-03/msg00976.html to
http://comments.gmane.org/gmane.comp.emulators.qemu/294066 . Dealing with sh2 is new to me, but it's also my day job these days. :)

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

(Now the reason _I_ thought you'd reject it had more to do with not having converted it to device tree yet, and things on that level. But I

Sh is an existing supported architecture, so DT is not a hard requirement.

Yeah, but new board... And it's the right thing to do.

I think convert DT is best way.

It looks don't use SH compatible peripherals.
I think if it's a SH compatible, it's better to maintain the platform_device structure.
But use incompatible peripherals (So need new platform_device), It's difficult to maintain it.

I trying SE7619 target convert to DT. It works fine. So no problem in 0PF platform DT support.

Quoted 24 lines
Quoted 2 lines

If you would have waited until after the removal of sh, it would be much harder :-) (cfr. h8300, but Sato-san did a great job there, with DT, CCF, ...)

Indeed he did. We had lunch with him when I was in Japan a couple weeks ago.

I've got the references I need to do this, just... lots of shoveling on a lot of fronts to do right now. (And I mentioned like 3 other things I already know I need to fix in the 0/2 message.)

Quoted 6 lines
Quoted 3 lines

wanted to get it out there so people outside $DAYJOB can test the hardware. We did a linuxcon japan presentation which lwn.net covered, and we're getting pokes about "where can I download this", so...)

It's great to hear there's so much interest in this! Let's hope this will attract more actual contributors...

The "where can I download this" is now the developer tab of 0pf.org by the way. And the mailing lists are on lists.nommu.org.

I'll try to submit an updated patch set in the next couple days.

Thanks,

Rob

Signature · 4 lines
Yoshinori Sato
<[email protected]>
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