ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously
PATCH v2 1/2 ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously, because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel.
---
Changes since v1:
- Move the clock assignment inside &clks as suggested by Philipp
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +7 -0
@@ -141,6 +141,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>;
Signature · 1 line
1.9.1
PATCH v2 2/2 clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl
Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board.
Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL.
Based on the configuration done in the FSL kernel.
---
Changes since v1:
- None. Newly introduced.
drivers/clk/imx/clk-imx6q.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/clk/imx/clk-imx6q.c +5 -0
@@ -494,6 +494,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)clk_set_parent (clk[IMX6QDL_CLK_LDB_DI1_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]); } +if (clk_on_imx6dl ()) { +clk_set_rate (clk[IMX6QDL_CLK_PLL3_PFD1_540M ],540000000 ); +clk_set_parent (clk[IMX6QDL_CLK_IPU1_SEL ], clk[IMX6QDL_CLK_PLL3_PFD1_540M ]); + } +clk_set_parent (clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);clk_set_parent (clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);clk_set_parent (clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);
Signature · 1 line
1.9.1
PATCH v2 2/2 clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl
Hi Fabio,
Quoted 21 lines · Fabio Estevam
Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board.
Fix this usecase by setting
IMX6QDL_CLK_PLL3_PFD1_540Mto 540MHz and also by setting it as the parent ofIMX6QDL_CLK_IPU1_SEL.Based on the configuration done in the FSL kernel.
Signed-off-by Fabio Estevam <[email protected]>---
Changes since v1:
- None. Newly introduced.drivers/clk/imx/clk-imx6q.c | 5 +++++ 1 file changed, 5 insertions(+)drivers/clk/imx/clk-imx6q.c +0
-0
drivers/clk/imx/clk-imx6q.c static void __init imx6q_clocks_init(struct device_node *ccm_node) · line 498
Quoted 5 lines
drivers/clk/imx/clk-imx6q.c +2
-0@@ -494,6 +494,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)clk_set_parent (clk[IMX6QDL_CLK_LDB_DI1_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]); } +if (clk_on_imx6dl ()) { +clk_set_rate (clk[IMX6QDL_CLK_PLL3_PFD1_540M ],540000000 );
I believe here IMX6QDL_CLK_PLL3_PFD1_540M rate can be set independently of SoC flavour.
drivers/clk/imx/clk-imx6q.c static void __init imx6q_clocks_init(struct device_node *ccm_node) · line 504
Quoted 7 lines
drivers/clk/imx/clk-imx6q.c +3
-0+clk_set_parent (clk[IMX6QDL_CLK_IPU1_SEL ], clk[IMX6QDL_CLK_PLL3_PFD1_540M ]); + } +clk_set_parent (clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);clk_set_parent (clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);clk_set_parent (clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL ], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV ]);
--
With best wishes,
Vladimir
PATCH v2 1/2 ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously
In reply to Fabio EstevamAm Donnerstag, den 25.06.2015, 11:17 -0300 schrieb Fabio Estevam:
Quoted 10 lines
Currently it is not possible to have HDMI and LVDS working simultaneously, because both ports try to use PLL5.
Move the LVDS clock parent to
PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources.With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by Fabio Estevam <[email protected]>
regards
Philipp