sunxi: misc fixes and SinA33 support

Hi,

This series adds support for Sinlinx SinA33, an A33 devboard, while also fixing some things I encountered along the way.

Patch 1 fixes build break when using PORT F UART0. (It seems no one uses it now that we have LCD support.)

Patch 2 fixes the RSB errors I ran into on my A33 devices.

Patch 3 adds support for UART0 on PB pin group, which is A33 specific.

Patch 4 syncs the sun8i dts files with the latest dts patches bound for 4.2.

Patch 5 adds a defconfig for the Sinlinx SinA33.

Regards
ChenYu

Chen-Yu Tsai (5):
sunxi: hardware-feature-specific function index defines for PORT F
UART0
sunxi: rsb: Enable R_PIO clock before configuring external pins
sunxi: Add support for UART0 in PB pin group on A33
sunxi: Sync sun8i dts files with the linux kernel
sunxi: Add Sinlinx SinA33 defconfig

 arch/arm/cpu/armv7/sunxi/board.c                   |  12 ++-
 arch/arm/cpu/armv7/sunxi/rsb.c                     |   5 +-
 arch/arm/dts/Makefile                              |   3 +-
 arch/arm/dts/sun8i-a23-a33.dtsi                    |  10 ++
 ...sun8i-a33.dtsi => sun8i-a33-sinlinx-sina33.dts} | 106 ++++++++++++++-------
 arch/arm/dts/sun8i-a33.dtsi                        |   8 ++
 arch/arm/include/asm/arch-sunxi/gpio.h             |   1 +
 board/sunxi/MAINTAINERS                            |   6 ++
 configs/Sinlinx_SinA33_defconfig                   |   8 ++
 9 files changed, 119 insertions(+), 40 deletions(-)
 copy arch/arm/dts/{sun8i-a33.dtsi => sun8i-a33-sinlinx-sina33.dts} (56%)
 create mode 100644 configs/Sinlinx_SinA33_defconfig

2.1.4

Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions.

---
 arch/arm/cpu/armv7/sunxi/board.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index 0fe641f..5a4e64b 100644
@@ -47,11 +47,11 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
 #if defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
 #else
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
 #endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))

2.1.4

The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL.

Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board.

Reordering the calls fixed this.

---
 arch/arm/cpu/armv7/sunxi/rsb.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

index f115a9c..6fd11f1 100644
@@ -60,11 +60,12 @@ int rsb_init(void)
 	struct sunxi_rsb_reg * const rsb =
 		(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
-	rsb_cfg_io();
-
 	/* Enable RSB and PIO clk, and de-assert their resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 
+	/* Setup external pins */
+	rsb_cfg_io();
+
 	writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
 	rsb_set_clk();
 

2.1.4

Thanks!
Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The A33 adds a pinmux function for UART0 in the PB pin group.

---
 arch/arm/cpu/armv7/sunxi/board.c       | 4 ++++
 arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
 2 files changed, 5 insertions(+)

index 5a4e64b..f01846e 100644
@@ -66,6 +66,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);

index b628fee..f30e76f 100644
@@ -156,6 +156,7 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
+#define SUN8I_A33_GPB_UART0	3
 
 #define SUNXI_GPC_NAND		2
 

2.1.4

Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files.

---
 arch/arm/dts/sun8i-a23-a33.dtsi                    |  10 ++
 ...sun8i-a33.dtsi => sun8i-a33-sinlinx-sina33.dts} | 106 ++++++++++++++-------
 arch/arm/dts/sun8i-a33.dtsi                        |   8 ++
 3 files changed, 91 insertions(+), 33 deletions(-)
 copy arch/arm/dts/{sun8i-a33.dtsi => sun8i-a33-sinlinx-sina33.dts} (56%)

index faea94e..7abd0ae 100644
@@ -366,6 +366,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			i2c0_pins_a: i2c0 at 0 {
 				allwinner,pins = "PH2", "PH3";
 				allwinner,function = "i2c0";

index 9b43bc6..85ee080 100644
@@ -86,4 +86,12 @@
 	compatible = "allwinner,sun8i-a33-pinctrl";
 	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+	uart0_pins_b: uart0 at 1 {
+		allwinner,pins = "PB0", "PB1";
+		allwinner,function = "uart0";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 };

2.1.4

Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers.

---
 arch/arm/dts/Makefile            | 3 ++-
 board/sunxi/MAINTAINERS          | 6 ++++++
 configs/Sinlinx_SinA33_defconfig | 8 ++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 configs/Sinlinx_SinA33_defconfig

index 9c735c6..bbca94f 100644
@@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
-	sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
+	sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb \
+	sun8i-a33-sinlinx-sina33.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb

index 7a42055..1f12a64 100644
@@ -162,6 +162,12 @@ M:	Siarhei Siamashka <[email protected]>
 S:	Maintained
 F:	configs/MSI_Primo81_defconfig
 
+SINLINX SINA33 BOARD
+M:	Chen-Yu Tsai <[email protected]>
+S:	Maintained
+F:	configs/Sinlinx_SinA33_defconfig
+W:	http://linux-sunxi.org/Sinlinx_SinA33
+
 TZX-Q8-713B7 BOARD
 M:	Paul Kocialkowski <[email protected]>
 S:	Maintained

new file mode 100644
index 0000000..8612625
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=15291
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
+CONFIG_SPL=y
+CONFIG_AXP221_ALDO1_VOLT=3000

2.1.4

Hi,

Thanks, I've merged all 5 and just send a pull-req out to get these included into v2015.07 (given the bug-fix nature of the first 2 patches).

Regards,

Hans