mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

-----Original Message-----
From: Priyanka Jain [mailto:Priyanka.Jain at freescale.com]
Sent: Friday, June 05, 2015 12:59 PM
To: u-boot at lists.denx.de
Cc: Sun York-R58495; Jain Priyanka-B32167; Ciubotariu Codrin Constantin-B43658; Wang Dongsheng-B40534
Subject: [PATCH][v7] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM

Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU

Signed-off-by Priyanka Jain <[email protected]>

Signed-off-by Codrin Ciubotariu <[email protected]>

Signed-off-by Wang Dongsheng <[email protected]>

---
changes from v2:
- adds SGMII suport using CPLD
- removes extra endif
changes from v3:
- removes checkpatch error
changes from v4:
- wrong use of defined MACRO in eth.c file, adds macro properly changes from
v5:
- updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg
- update DDR settings
changes from v6:
- update DDR settings, config files, cpld code, README
- Add QGMII phy addr configs, update DIU_SEL value

 board/freescale/t104xrdb/MAINTAINERS     |    8 +++
 board/freescale/t104xrdb/README          |   87 ++++++++++++++++++++++++++++-
 board/freescale/t104xrdb/cpld.c          |    4 ++
 board/freescale/t104xrdb/cpld.h          |    6 ++
 board/freescale/t104xrdb/ddr.c           |   10 ++++
 board/freescale/t104xrdb/ddr.h           |    9 +++-
 board/freescale/t104xrdb/eth.c           |   20 ++++++-
 board/freescale/t104xrdb/t1040d4_rcw.cfg |    7 +++
 board/freescale/t104xrdb/t1042d4_rcw.cfg |    7 +++
 board/freescale/t104xrdb/t104xrdb.c      |   32 +++++++++++
 configs/T1040D4RDB_NAND_defconfig        |    5 ++
 configs/T1040D4RDB_SDCARD_defconfig      |    5 ++
 configs/T1040D4RDB_SPIFLASH_defconfig    |    5 ++
 configs/T1040D4RDB_defconfig             |    4 ++
 configs/T1042D4RDB_NAND_defconfig        |    5 ++
 configs/T1042D4RDB_SDCARD_defconfig      |    5 ++
 configs/T1042D4RDB_SPIFLASH_defconfig    |    5 ++
 configs/T1042D4RDB_defconfig             |    4 ++
 include/configs/T104xRDB.h               |   64 ++++++++++++++++++----
 19 files changed, 276 insertions(+), 16 deletions(-)  create mode 100644
board/freescale/t104xrdb/t1040d4_rcw.cfg
 create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg
 create mode 100644 configs/T1040D4RDB_NAND_defconfig  create mode 100644
configs/T1040D4RDB_SDCARD_defconfig
 create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
 create mode 100644 configs/T1040D4RDB_defconfig  create mode 100644
configs/T1042D4RDB_NAND_defconfig  create mode 100644
configs/T1042D4RDB_SDCARD_defconfig
 create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
 create mode 100644 configs/T1042D4RDB_defconfig

board/freescale/t104xrdb/MAINTAINERS +8 -0

index 13d9be9..32e044f 100644
@@ -6,7 +6,13 @@ F:	include/configs/T104xRDB.h
 F:	configs/T1040RDB_defconfig
 F:	configs/T1040RDB_NAND_defconfig
 F:	configs/T1040RDB_SPIFLASH_defconfig
+F:	configs/T1040D4RDB_defconfig
+F:	configs/T1040D4RDB_NAND_defconfig
+F:	configs/T1040D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_defconfig
+F:	configs/T1042D4RDB_defconfig
+F:	configs/T1042D4RDB_NAND_defconfig
+F:	configs/T1042D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_PI_defconfig
 F:	configs/T1042RDB_PI_NAND_defconfig
 F:	configs/T1042RDB_PI_SPIFLASH_defconfig

@@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD
 #M:	-
 S:	Maintained
 F:	configs/T1040RDB_SDCARD_defconfig
+F:	configs/T1040D4RDB_SDCARD_defconfig
+F:	configs/T1042D4RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
 
 T1040RDB_SECURE_BOOT BOARD

board/freescale/t104xrdb/README +0 -0

index ac95b5e..b9d2212 100644
@@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the

T1042 SoC.
(a personality of T1040 SoC). The board is similar to T1040RDB but is designed
specially with low power features targeted for Printing Image Market.

board/freescale/t104xrdb/README +11 -0

+The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory and some enhancements
+
+The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory
+    - Support for 0x86 serdes protocol which can support following interfaces
+        - 2 RGMII's on DTSEC4, DTSEC5
+        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
+
 Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
 -------------------------------------------------------------------------
 Board		Si		Protocol		Targeted Market

@@ -19,6 +30,8 @@ Board		Si		Protocol		Targeted

Market
T1040RDB T1040 0x66 Networking
T1040RDB T1042 0x86 Networking
T1042RDB_PI T1042 0x06 Printing & Imaging

board/freescale/t104xrdb/README +2 -0

+T1040D4RDB	T1040		0x66                    Networking
+T1042D4RDB	T1042		0x86                    Networking
 
 
 T1040 SoC Overview

@@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and

features:

T1040 SoC Personalities
-------------------------

board/freescale/t104xrdb/README +0 -1

-
 T1022 Personality:
 T1022 is a reduced personality of T1040 with less core/clusters.

@@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB  Please note QE Firmware

is only valid for T1040RDB

board/freescale/t104xrdb/README +73 -2

-Switch Settings: (ON is 0, OFF is 1)
-===============
+Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
+==========================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111011
+SW3: 11100001
+
 NAND boot SW setting:
 SW1: 10001000
 SW2: 00111011

@@ -284,3 +301,67 @@ SD boot SW setting:
 SW1: 00100000
 SW2: 00111011
 SW3: 11100001
+
+Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
+=============================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111001
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
+
+PBL-based image generation
+==========================
+Changes only the required register bit in in PBI commands.
+
+Provides reference code which might needs some modification as per
+requirement.
+example:
+By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file which
+needs to be changed for SPI and SD.
+
+For SD-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg
+type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 6c027000 01000000
+
+2. SD does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0
+
+For SPI-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg
+type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 5c027000 01000000
+
+2. SPI does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0

board/freescale/t104xrdb/cpld.c +4 -0

index df0e348..0ce4e47 100644
@@ -69,7 +69,11 @@ static void cpld_dump_regs(void)
 	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
 	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
 	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
+#if defined(CONFIG_T104XD4RDB)
+	printf("int_mask	 = 0x%02x\n", CPLD_READ(int_mask));
+#else
 	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+#endif
 	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
 	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
 	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));

board/freescale/t104xrdb/cpld.h +4 -0

index 0da9a01..2fb4105 100644
@@ -21,7 +21,11 @@ struct cpld_data {
 	u8 int_status;		/* 0x12 - Interrupt status Register */
 	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
 	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
+#if defined(CONFIG_T104XD4RDB)
+	u8 int_mask;		/* 0x15 - Interrupt mask Register */
+#else
 	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+#endif
 	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
 	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
 	u8 boot_override;	/* 0x18 - Boot override register */

@@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value);  #define

CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\

board/freescale/t104xrdb/cpld.h +2 -0

 		cpld_write(offsetof(struct cpld_data, reg), value)
+#define MISC_CTL_SG_SEL		0x80
+#define MISC_CTL_AURORA_SEL	0x02

board/freescale/t104xrdb/ddr.c +9 -0

index e1148e5..cf79d2d 100644
@@ -75,7 +75,11 @@ found:
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->half_strength_driver_enable = 1; #else
 	popts->half_strength_driver_enable = 0;
+#endif
 	/*
 	 * Write leveling override
 	 */

@@ -91,8 +95,14 @@ found:
 	popts->zq_en = 1;
 
 	/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+		DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #if defined(CONFIG_DEEP_SLEEP)

board/freescale/t104xrdb/ddr.h +8 -1

index ab1c32d..b9c02f7 100644
@@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+#elif defined(CONFIG_SYS_FSL_DDR3)
 	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
 	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
 	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},

@@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = {
 	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
 	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
 	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+#else
+#error DDR type not defined
+#endif
 	{}
 };
 
+#endif
+
 static const struct board_specific_parameters *udimms[] = {
 	udimm0,
 };
-#endif

board/freescale/t104xrdb/eth.c +18 -2

index 7581a4cd..71d0457 100644
@@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis)
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 		case PHY_INTERFACE_MODE_SGMII:
-			/* T1040RDB only supports SGMII on DTSEC3 */
+			/* T1040RDB & T1040D4RDB only supports SGMII on
+			 * DTSEC3
+			 */
 			fm_info_set_phy_address(FM1_DTSEC3,
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;

@@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis)
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
+#ifdef CONFIG_T1042D4RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+			 *  & DTSEC3
+			 */
+			if (FM1_DTSEC1 == i)
+				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+			if (FM1_DTSEC2 == i)
+				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+#endif
 		case PHY_INTERFACE_MODE_RGMII:
 			if (FM1_DTSEC4 == i)
 				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git

a/board/freescale/t104xrdb/t1040d4_rcw.cfg
b/board/freescale/t104xrdb/t1040d4_rcw.cfg
new file mode 100644
index 0000000..c1034b3

board/freescale/t104xrdb/t1040d4_rcw.cfg new file +7 -0

@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000

board/freescale/t104xrdb/t1042d4_rcw.cfg new file +7 -0

new file mode 100644
index 0000000..9e0ee27
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000

board/freescale/t104xrdb/t104xrdb.c +31 -0

index c34eea6..d982dfc 100644
@@ -28,7 +28,11 @@ int checkboard(void)
 	struct cpu_type *cpu = gd->arch.cpu;
 	u8 sw;
 
+#ifdef CONFIG_T104XD4RDB
+	printf("Board: %sD4RDB\n", cpu->name); #else
 	printf("Board: %sRDB\n", cpu->name);
+#endif
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
 

@@ -88,6 +92,34 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+	printf("SERDES Reference : 0x%X\n", srds_s1);
+
+	/* select SGMII*/
+	if (srds_s1 == 0x86)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL);
+
+	/* select SGMII and Aurora*/
+	if (srds_s1 == 0x8E)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_T1040D4RDB)
+	/* Mask all CPLD interrupt sources, except QSGMII interrupts */
+	if (CPLD_READ(sw_ver) < 0x03) {
+		debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+		      CPLD_READ(sw_ver));
+	} else {
+		CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+			   ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+	}
+#endif
+
 	return 0;
 }
 

configs/T1040D4RDB_NAND_defconfig new file +2 -0

new file mode 100644
index 0000000..c82fde2
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T10

4XD4RDB,SYS_FSL_DDR4"

configs/T1040D4RDB_NAND_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SDCARD_defconfig new file +2 -0

new file mode 100644
index 0000000..459b98d
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T

104XD4RDB,SYS_FSL_DDR4"

configs/T1040D4RDB_SDCARD_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_SPIFLASH_defconfig new file +2 -0

new file mode 100644
index 0000000..e2654b8
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH

,T104XD4RDB,SYS_FSL_DDR4"

configs/T1040D4RDB_SPIFLASH_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1040D4RDB_defconfig new renamed from configs/T1040D4RDB_defconfig +0 -0

file mode 100644 index 0000000..f9a23cf

configs/T1040D4RDB_defconfig new file +4 -0

@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_NAND_defconfig new file +2 -0

new file mode 100644
index 0000000..146f4ad
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T10

4XD4RDB,SYS_FSL_DDR4"

configs/T1042D4RDB_NAND_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SDCARD_defconfig new file +2 -0

new file mode 100644
index 0000000..2273637
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T

104XD4RDB,SYS_FSL_DDR4"

configs/T1042D4RDB_SDCARD_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_SPIFLASH_defconfig new file +2 -0

new file mode 100644
index 0000000..2edf310
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH

,T104XD4RDB,SYS_FSL_DDR4"

configs/T1042D4RDB_SPIFLASH_defconfig new file +3 -0

+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

configs/T1042D4RDB_defconfig new renamed from configs/T1042D4RDB_defconfig +0 -0

file mode 100644 index 0000000..3802637

configs/T1042D4RDB_defconfig new file +4 -0

@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y

include/configs/T104xRDB.h index renamed from include/configs/T104xRDB.h +0 -0

6cc95ef..e856c17 100644

include/configs/T104xRDB.h +0 -0

@@ -29,6 +29,14 @@
 #ifdef CONFIG_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW

$(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
#endif

include/configs/T104xRDB.h +54 -10

+#ifdef CONFIG_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
+#endif
+#ifdef CONFIG_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
+#endif
 
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT

@@ -220,7 +228,9 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3
+#endif
 
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51

@@ -278,8 +288,23 @@
 #define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
 #define CPLD_LBMAP_RESET		0xFF
 #define CPLD_LBMAP_SHIFT		0x03
-#ifdef CONFIG_T1042RDB_PI
+
+#if defined(CONFIG_T1042RDB_PI)
 #define CPLD_DIU_SEL_DFP		0x80
+#elif defined(CONFIG_T1042D4RDB)
+#define CPLD_DIU_SEL_DFP		0xc0
+#endif
+
+#if defined(CONFIG_T1040D4RDB)
+#define CPLD_INT_MASK_ALL		0xFF
+#define CPLD_INT_MASK_THERM		0x80
+#define CPLD_INT_MASK_DVI_DFP		0x40
+#define CPLD_INT_MASK_QSGMII1		0x20
+#define CPLD_INT_MASK_QSGMII2		0x10
+#define CPLD_INT_MASK_SGMI1		0x08
+#define CPLD_INT_MASK_SGMI2		0x04
+#define CPLD_INT_MASK_TDMR1		0x02
+#define CPLD_INT_MASK_TDMR2		0x01
 #endif
 
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000

@@ -447,7 +472,7 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 /* Video */
 #define CONFIG_FSL_DIU_FB
 

@@ -492,11 +517,11 @@
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 #define I2C_MUX_CH_DEFAULT      0x8
 #endif
 
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR		0x38
 #define CONFIG_SYS_I2C_DVI_ADDR		0x75

@@ -665,7 +690,7 @@
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 #define CONFIG_QE
 #define CONFIG_U_QE
 #endif

@@ -694,7 +719,7 @@
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_QE_FW_ADDR		0x130000
 #elif defined(CONFIG_SDCARD)

@@ -719,17 +744,32 @@
 
 #ifdef CONFIG_FMAN_ENET
 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#endif
+
+#ifdef CONFIG_T104XD4RDB
+#define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
+#define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
+#else
+#define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
-#define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR		0x02
 
 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 #define CONFIG_VSC9953
 #define CONFIG_VSC9953_CMD
+#ifdef CONFIG_T1040RDB
 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
+#else
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
+#endif
 #endif
 
 #define CONFIG_MII		/* MII PHY management */

@@ -841,6 +881,10 @@
 #define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
 #elif defined(CONFIG_T1042RDB)
 #define FDTFILE		"t1042rdb/t1042rdb.dtb"
+#elif defined(CONFIG_T1040D4RDB)
+#define FDTFILE		"t1042rdb/t1040d4rdb.dtb"
+#elif defined(CONFIG_T1042D4RDB)
+#define FDTFILE		"t1042rdb/t1042d4rdb.dtb"
 #endif
 
 #ifdef CONFIG_FSL_DIU_FB
--

1.7.4.1

Hi,

Just a heads up, I already sent a patch for T1040D4RDB regarding CPLD configuration: mpc85xx/T1040D4RDB: Disable all CPLD interrupts, except QSGMI1 and QSGMI2. Since this patch includes the CPLD configurations, I guess mine will become deprecated.

Best regards,
Codrin

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM

Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU

Signed-off-by Priyanka Jain <[email protected]>

Signed-off-by Codrin Ciubotariu <[email protected]>

Signed-off-by Wang Dongsheng <[email protected]>

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM

Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU

Signed-off-by Priyanka Jain <[email protected]>

Signed-off-by Codrin Ciubotariu <[email protected]>

Signed-off-by Wang Dongsheng <[email protected]>

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM

Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU

Signed-off-by Priyanka Jain <[email protected]>

Signed-off-by Codrin Ciubotariu <[email protected]>

Signed-off-by Wang Dongsheng <[email protected]>

---
changes from v2:
- adds SGMII suport using CPLD
- removes extra endif
changes from v3:
- removes checkpatch error
changes from v4:
- wrong use of defined MACRO in eth.c file, adds macro properly
changes from v5:
- updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg
- update DDR settings
changes from v6:
- update DDR settings, config files, cpld code, README
- Add QGMII phy addr configs, update DIU_SEL value