spi: cadence_qspi: sram depth from DT & fix for FIFO width
Subsystems (2)
v3 cover spi: cadence_qspi: sram depth from DT & fix for FIFO width
This patchset adds support to get controller sram size from device tree, fix to support different FIFO widths & adds dt binding doc.
Also this patchset enables cadence qspi controller for stv0991 soc, saves environment in spi flash & moves CONFIG_OF in the defconfig file.
Changes in v3:
- Clubbed two patchsets:
1. [v2 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width
2. [v2 0/6] stv0991: enable cadence qspi controller & spi flash
Changes in v2:
- fix the checkpatch error.
Vikas Manocha (10):
stv0991: enable saving enrironment in spi flash
stv0991: move OF_CONTROL config to defconfig
stv0991: remove define CONFIG_OF_SEPARATE from board file
stv0991: configure clock & pad muxing for qspi
stv0991: enable cadence qspi controller & spi flash
stv0991: configure device tree for cadence qspi & flash
spi: cadence_qspi: move the sram partition in init
spi: cadence_qspi: get sram size from device tree
spi: cadence_qspi: support FIFO width other than 4 bytes
spi: cadence_qspi: add device tree binding doc
arch/arm/cpu/armv7/stv0991/clock.c | 4 +- arch/arm/cpu/armv7/stv0991/pinmux.c | 5 ++ arch/arm/dts/socfpga.dtsi | 4 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - arch/arm/dts/stv0991.dts | 31 ++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 15 +++++ arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 9 +++ arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 2 + board/st/stv0991/stv0991.c | 8 +++ configs/stv0991_defconfig | 2 +- doc/device-tree-bindings/spi/spi-cadence.txt | 28 +++++++++ drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 62 ++++++++------------ include/configs/stv0991.h | 24 +++++++- 15 files changed, 152 insertions(+), 45 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt
Signature · 1 line
1.7.9.5
PATCH v3 1/10 stv0991: enable saving enrironment in spi flash
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig | 1 - include/configs/stv0991.h | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-)
configs/stv0991_defconfig +0 -1
@@ -7,7 +7,6 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y
include/configs/stv0991.h +3 -1
@@ -23,7 +23,9 @@#define PHYS_SDRAM_1_SIZE 0x00198000#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET 0x30000#define CONFIG_ENV_ADDR \ (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)#define CONFIG_SYS_MAXARGS 16
Signature · 1 line
1.7.9.5
PATCH v3 2/10 stv0991: move OF_CONTROL config to defconfig
In reply to Vikas Manocha---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig | 1 + include/configs/stv0991.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-)
configs/stv0991_defconfig +1 -0
@@ -11,3 +11,4 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_OF_CONTROL=y
include/configs/stv0991.h +0 -1
@@ -75,6 +75,5 @@#define CONFIG_BOOTCOMMAND "go 0x40040000"#define CONFIG_OF_SEPARATE -#define CONFIG_OF_CONTROL #define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */
Signature · 1 line
1.7.9.5
PATCH v3 3/10 stv0991: remove define CONFIG_OF_SEPARATE from board file
In reply to Vikas ManochaCONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing this define from the board file to avoid multiple definition warning.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
include/configs/stv0991.h | 1 - 1 file changed, 1 deletion(-)
include/configs/stv0991.h +0 -1
@@ -74,6 +74,5 @@#define CONFIG_BOOTDELAY 3#define CONFIG_BOOTCOMMAND "go 0x40040000" -#define CONFIG_OF_SEPARATE #define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */
Signature · 1 line
1.7.9.5
PATCH v3 4/10 stv0991: configure clock & pad muxing for qspi
In reply to Vikas Manochastv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2:
- removed checkpatch.pl error.
arch/arm/cpu/armv7/stv0991/clock.c | 4 +++- arch/arm/cpu/armv7/stv0991/pinmux.c | 5 +++++ arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 15 +++++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 9 +++++++++ arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 2 ++ board/st/stv0991/stv0991.c | 8 ++++++++ 6 files changed, 42 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/stv0991/clock.c +3 -1
@@ -33,7 +33,9 @@ void clock_setup(int peripheral)/* Clock selection for ethernet tx_clk & rx_clk*/ writel ((readl (&stv0991_cgu_regs->eth_ctrl) Ð_CLK_MASK ) |ETH_CLK_CTRL , &stv0991_cgu_regs->eth_ctrl); - +break ; +case QSPI_CLOCK_CFG : +writel (QSPI_CLK_CTRL , &stv0991_cgu_regs->qspi_freq);break ;default :break ;
arch/arm/cpu/armv7/stv0991/pinmux.c +5 -0
@@ -55,6 +55,11 @@ int stv0991_pinmux_config(int peripheral) ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);break ; +case QSPI_CS_CLK_PAD : +writel ((readl (&stv0991_creg->mux13) &FLASH_CS_NC_MASK ) | +CFG_FLASH_CS_NC , &stv0991_creg->mux13); +writel ((readl (&stv0991_creg->mux13) &FLASH_CLK_MASK ) | +CFG_FLASH_CLK , &stv0991_creg->mux13);default :break ; }
arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +15 -0
@@ -113,4 +113,19 @@ struct stv0991_cgu_regs {#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ | ETH_CLK_TX_EXT_PHY) +/* CGU qspi clock */ +#define DIV_HCLK1_SHIFT 9 +#define DIV_CRYP_SHIFT 6 +#define MDIV_QSPI_SHIFT 3 + +#define CLK_QSPI_OSC 0 +#define CLK_QSPI_MCLK 1 +#define CLK_QSPI_PLL1 2 +#define CLK_QSPI_PLL2 3 + +#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ + | 1 << DIV_CRYP_SHIFT \ + | 0 << MDIV_QSPI_SHIFT \ + | CLK_QSPI_OSC) +#endif
arch/arm/include/asm/arch-stv0991/stv0991_creg.h +9 -0
@@ -49,6 +49,15 @@ struct stv0991_creg {u32 vdd_comp1;/* offset 0x400 */ }; +/* CREG MUX 13 register */ +#define FLASH_CS_NC_SHIFT 4 +#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) +#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) + +#define FLASH_CLK_SHIFT 0 +#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) +#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) +/* CREG MUX 12 register */ #define GPIOC_30_MUX_SHIFT 24#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
arch/arm/include/asm/arch-stv0991/stv0991_periph.h +2 -0
@@ -18,6 +18,7 @@ enum periph_id {UART_GPIOC_30_31 =0 ,UART_GPIOB_16_17 ,ETH_GPIOB_10_31_C_0_4 , +QSPI_CS_CLK_PAD ,PERIPH_ID_I2C0 ,PERIPH_ID_I2C1 , PERIPH_ID_I2C2,
@@ -39,6 +40,7 @@ enum periph_id {enum periph_clock {UART_CLOCK_CFG =0 ,ETH_CLOCK_CFG , +QSPI_CLOCK_CFG , };#endif /* __ASM_ARM_ARCH_PERIPH_H */
board/st/stv0991/stv0991.c +8 -0
@@ -55,12 +55,20 @@ int board_eth_enable(void)return 0 ; } +int board_qspi_enable (void ) +{ +stv0991_pinmux_config (QSPI_CS_CLK_PAD ); +clock_setup (QSPI_CLOCK_CFG ); +return 0 ; +} +/* * Miscellaneous platform dependent initialisations */ int board_init (void ) {board_eth_enable (); +board_qspi_enable ();return 0 ; }
Signature · 1 line
1.7.9.5
PATCH v3 5/10 stv0991: enable cadence qspi controller & spi flash
In reply to Vikas ManochaThis patch does all the board configurations required to use the qspi controller & attached spi flash memory.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
include/configs/stv0991.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
include/configs/stv0991.h +18 -0
@@ -75,4 +75,22 @@#define CONFIG_BOOTCOMMAND "go 0x40040000"#define CONFIG_OF_LIBFDT + +/* ++ * QSPI support ++ */ +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ +#define CONFIG_DM_SPI +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_DECODER 0 +#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_CMD_SPI + +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_WINBOND /* WINBOND */ +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#endif +#endif /* __CONFIG_H */
Signature · 1 line
1.7.9.5
PATCH v3 6/10 stv0991: configure device tree for cadence qspi & flash
In reply to Vikas ManochaThis patch add the device tree entry for qspi controller & spi flash memory.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/dts/stv0991.dts | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
arch/arm/dts/stv0991.dts +34 -0
@@ -20,4 +20,38 @@ reg = <0x80406000 0x1000>; clock = <2700000>; }; + + aliases { + spi0 = "/spi at 80203000"; /* QSPI */ + }; + + qspi: spi at 80203000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80203000 0x100>, + <0x40000000 0x1000000>; + clocks = <3750000>; + ext-decoder = <0>; /* external decoder */ + num-cs = <4>; + fifo-depth = <256>; + bus-num = <0>; + status = "okay"; + + flash0: n25q32 at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; + }; };
Signature · 1 line
1.7.9.5
PATCH v3 7/10 spi: cadence_qspi: move the sram partition in init
In reply to Vikas ManochaThere is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
drivers/spi/cadence_qspi_apb.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-)
drivers/spi/cadence_qspi_apb.c +5 -11
@@ -38,10 +38,7 @@/* Controller sram size in word */ #define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_RESV_WORDS (2) -#define CQSPI_REG_SRAM_PARTITION_WR (1) -#define CQSPI_REG_SRAM_PARTITION_RD \ - (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)/* Transfer mode */
@@ -538,6 +535,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)/* Configure the remap address register, no remap */ writel (0 , plat->regbase +CQSPI_REG_REMAP ); +/* Indirect mode configurations */ +writel (CQSPI_REG_SRAM_PARTITION_RD , + plat->regbase +CQSPI_REG_SRAMPARTITION ); +/* Disable all interrupts */ writel (0 , plat->regbase +CQSPI_REG_IRQMASK );
@@ -700,10 +701,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,writel (((u32 )plat->ahbbase &CQSPI_INDIRECTTRIGGER_ADDR_MASK ), plat->regbase +CQSPI_REG_INDIRECTTRIGGER ); -/* Configure SRAM partition for read. */ -writel (CQSPI_REG_SRAM_PARTITION_RD , plat->regbase + -CQSPI_REG_SRAMPARTITION ); -/* Configure the opcode */ rd_reg = cmdbuf[0 ] <<CQSPI_REG_RD_INSTR_OPCODE_LSB ;
@@ -801,9 +798,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,writel (((u32 )plat->ahbbase &CQSPI_INDIRECTTRIGGER_ADDR_MASK ), plat->regbase +CQSPI_REG_INDIRECTTRIGGER ); -writel (CQSPI_REG_SRAM_PARTITION_WR , - plat->regbase +CQSPI_REG_SRAMPARTITION ); -/* Configure the opcode */ reg = cmdbuf[0 ] <<CQSPI_REG_WR_INSTR_OPCODE_LSB ;writel (reg, plat->regbase +CQSPI_REG_WR_INSTR );
Signature · 1 line
1.7.9.5
PATCH v3 8/10 spi: cadence_qspi: get sram size from device tree
In reply to Vikas Manochasram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 +----- 5 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/dts/socfpga.dtsi +1 -0
@@ -639,6 +639,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <128>; + sram-size = <128>; bus-num = <2>; status = "disabled"; };
arch/arm/dts/stv0991.dts +1 -0
@@ -35,6 +35,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <256>; + sram-size = <256>; bus-num = <0>; status = "okay";
drivers/spi/cadence_qspi.c +1 -0
@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tsd2d_ns =fdtdec_get_int (blob, subnode,"tsd2d-ns" ,255 ); plat->tchsh_ns =fdtdec_get_int (blob, subnode,"tchsh-ns" ,20 ); plat->tslch_ns =fdtdec_get_int (blob, subnode,"tslch-ns" ,20 ); + plat->sram_size =fdtdec_get_int (blob, node,"sram-size" ,128 ); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz,
drivers/spi/cadence_qspi.h +1 -0
@@ -25,6 +25,7 @@ struct cadence_spi_platdata {u32 tsd2d_ns;u32 tchsh_ns;u32 tslch_ns; +u32 sram_size; };struct cadence_spi_priv {
drivers/spi/cadence_qspi_apb.c +1 -5
@@ -36,9 +36,6 @@#define CQSPI_FIFO_WIDTH (4) -/* Controller sram size in word */ -#define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)/* Transfer mode */
@@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)writel (0 , plat->regbase +CQSPI_REG_REMAP );/* Indirect mode configurations */ -writel (CQSPI_REG_SRAM_PARTITION_RD , - plat->regbase +CQSPI_REG_SRAMPARTITION ); +writel ((plat->sram_size/2 ), plat->regbase +CQSPI_REG_SRAMPARTITION );/* Disable all interrupts */ writel (0 , plat->regbase +CQSPI_REG_IRQMASK );
Signature · 1 line
1.7.9.5
PATCH v3 8/10 spi: cadence_qspi: get sram size from device tree
Quoted 4 lines · Vikas Manocha
sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by Vikas Manocha <[email protected]>
Still have an issue - unable to apply.
Quoted 86 lines
Tested-by Stefan Roese <[email protected]>---
Changes in v3: Rebased to spi-next-dev
Changes in v2: Nonearch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 +----- 5 files changed, 5 insertions(+), 5 deletions(-)arch/arm/dts/socfpga.dtsi +1
-0@@ -639,6 +639,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <128>; + sram-size = <128>; bus-num = <2>; status = "disabled"; };arch/arm/dts/stv0991.dts +1
-0@@ -35,6 +35,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <256>; + sram-size = <256>; bus-num = <0>; status = "okay";drivers/spi/cadence_qspi.c +1
-0@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tsd2d_ns =fdtdec_get_int (blob, subnode,"tsd2d-ns" ,255 ); plat->tchsh_ns =fdtdec_get_int (blob, subnode,"tchsh-ns" ,20 ); plat->tslch_ns =fdtdec_get_int (blob, subnode,"tslch-ns" ,20 ); + plat->sram_size =fdtdec_get_int (blob, node,"sram-size" ,128 ); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz,drivers/spi/cadence_qspi.h +1
-0@@ -25,6 +25,7 @@ struct cadence_spi_platdata {u32 tsd2d_ns;u32 tchsh_ns;u32 tslch_ns; +u32 sram_size; };struct cadence_spi_priv {drivers/spi/cadence_qspi_apb.c +1
-6@@ -36,9 +36,6 @@#define CQSPI_FIFO_WIDTH (4) -/* Controller sram size in word */ -#define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)/* Transfer mode */ @@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)writel (0 , plat->regbase +CQSPI_REG_REMAP );/* Indirect mode configurations */ -writel (CQSPI_REG_SRAM_PARTITION_RD , - plat->regbase +CQSPI_REG_SRAMPARTITION ); +writel ((plat->sram_size/2 ), plat->regbase +CQSPI_REG_SRAMPARTITION );/* Disable all interrupts */ writel (0 , plat->regbase +CQSPI_REG_IRQMASK ); --
Quoted 1 line
1.7.9.5
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v3 9/10 spi: cadence_qspi: support FIFO width other than 4 bytes
In reply to Vikas ManochaThis patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops.
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: Fixed the checkpatch.pl error
drivers/spi/cadence_qspi_apb.c | 46 ++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-)
drivers/spi/cadence_qspi_apb.c +23 -23
@@ -200,18 +200,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,unsigned int *dest_ptr = (unsigned int *)dest;unsigned int *src_ptr = (unsigned int *)src_ahb_addr; -while (remaining >0 ) { -if (remaining >=CQSPI_FIFO_WIDTH ) { - *dest_ptr =readl (src_ptr); - remaining -=CQSPI_FIFO_WIDTH ; - }else { -/* dangling bytes */ - temp =readl (src_ptr); -memcpy (dest_ptr, &temp, remaining); -break ; - } +while (remaining >=sizeof (dest_ptr)) { + *dest_ptr =readl (src_ptr); + remaining -=sizeof (src_ptr); dest_ptr++; } +if (remaining) { +/* dangling bytes */ + temp =readl (src_ptr); +memcpy (dest_ptr, &temp, remaining); + }return ; }
@@ -219,24 +217,26 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,static void cadence_qspi_apb_write_fifo_data (const void *dest_ahb_addr,const void *src,unsigned int bytes) { -unsigned int temp; +unsigned int temp =0 ; +int i;int remaining = bytes;unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;unsigned int *src_ptr = (unsigned int *)src; -while (remaining >0 ) { -if (remaining >=CQSPI_FIFO_WIDTH ) { -writel (*src_ptr, dest_ptr); - remaining -=sizeof (unsigned int ); - }else { -/* dangling bytes */ -memcpy (&temp, src_ptr, remaining); -writel (temp, dest_ptr); -break ; - } - src_ptr++; +while (remaining >=CQSPI_FIFO_WIDTH ) { +for (i =CQSPI_FIFO_WIDTH /sizeof (src_ptr) -1 ; i >=0 ; i--) +writel (*(src_ptr+i), dest_ptr+i); + src_ptr +=CQSPI_FIFO_WIDTH /sizeof (src_ptr); + remaining -=CQSPI_FIFO_WIDTH ; + } +if (remaining) { +/* dangling bytes */ + i = remaining/sizeof (dest_ptr); +memcpy (&temp, src_ptr+i, remaining %sizeof (dest_ptr)); +writel (temp, dest_ptr+i); +for (--i; i >=0 ; i--) +writel (*(src_ptr+i), dest_ptr+i); } -return ; }
Signature · 1 line
1.7.9.5
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
In reply to Vikas ManochaThis patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the device trees using this controller.
---
Changes in v3: added new
arch/arm/dts/socfpga.dtsi | 3 --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - arch/arm/dts/stv0991.dts | 4 ---- doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++++++++++++++++++ 4 files changed, 28 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt
arch/arm/dts/socfpga.dtsi +0 -3
@@ -636,9 +636,6 @@ <0xffa00000 0x1000>; interrupts = <0 151 4>; clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <128>; sram-size = <128>; bus-num = <2>; status = "disabled";
arch/arm/dts/socfpga_cyclone5_socrates.dts +0 -1
@@ -56,7 +56,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>;
arch/arm/dts/stv0991.dts +0 -4
@@ -32,9 +32,6 @@ reg = <0x80203000 0x100>, <0x40000000 0x1000000>; clocks = <3750000>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <256>; sram-size = <256>; bus-num = <0>; status = "okay";
@@ -48,7 +45,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>;
doc/device-tree-bindings/spi/spi-cadence.txt new file +28 -0
@@ -0,0 +1,28 @@ +Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size. +- status : enable in requried dts. + +connected flash properties +-------------------------- + +- spi-max-frequency : Max supported spi frequency. +- page-size : Flash page size. +- block-size : Flash memory block size. +- tshsl-ns : Added delay in master reference clocks (ref_clk) for + the length that the master mode chip select outputs + are de-asserted between transactions. +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one + chip select being de-activated and the activation of + another. +- tchsh-ns : Delay in master reference clocks between last bit of + current transaction and de-asserting the device chip + select (n_ss_out). +- tslch-ns : Delay in master reference clocks between setting + n_ss_out low and first bit transfer
Signature · 1 line
1.7.9.5
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Quoted 70 lines · Vikas Manocha
This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the device trees using this controller.
Signed-off-by Vikas Manocha <[email protected]>---
Changes in v3: added new
arch/arm/dts/socfpga.dtsi | 3 --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - arch/arm/dts/stv0991.dts | 4 ---- doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++++++++++++++++++ 4 files changed, 28 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txtarch/arm/dts/socfpga.dtsi +0
-3@@ -636,9 +636,6 @@ <0xffa00000 0x1000>; interrupts = <0 151 4>; clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <128>; sram-size = <128>; bus-num = <2>; status = "disabled";arch/arm/dts/socfpga_cyclone5_socrates.dts +0
-1@@ -56,7 +56,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>;arch/arm/dts/stv0991.dts +0
-4@@ -32,9 +32,6 @@ reg = <0x80203000 0x100>, <0x40000000 0x1000000>; clocks = <3750000>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <256>; sram-size = <256>; bus-num = <0>; status = "okay";@@ -48,7 +45,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>;doc/device-tree-bindings/spi/spi-cadence.txt new file +0
-0
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 9 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-0@@ -0,0 +1,28 @@ +Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.
? bus-num
Quoted 10 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +10
-0+- status : enable in requried dts. + +connected flash properties +-------------------------- + +- spi-max-frequency : Max supported spi frequency. +- page-size : Flash page size. +- block-size : Flash memory block size. +- tshsl-ns : Added delay in master reference clocks (ref_clk) for + the length that the master mode chip select outputs
doc/device-tree-bindings/spi/spi-cadence.txt
Quoted 10 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-1+ are de-asserted between transactions. +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one + chip select being de-activated and the activation of + another. +- tchsh-ns : Delay in master reference clocks between last bit of + current transaction and de-asserting the device chip + select (n_ss_out). +- tslch-ns : Delay in master reference clocks between setting + n_ss_out low and first bit transfer --
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Thanks Jagan,
Quoted 85 lines
-----Original Message-----
From: Jagan Teki [mailto:jteki at openedev.com]
Sent: Monday, June 29, 2015 11:29 PM
To: Vikas MANOCHA
Cc: u-boot at lists.denx.de; Stefan Roese
Subject: Re: [U-Boot] [v3 10/10] spi:cadence_qspi: add device tree binding docQuoted 5 lines · Vikas Manocha
This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the device trees using this controller.
Signed-off-by Vikas Manocha <[email protected]>Quoted 8 lines
---
Changes in v3: added new
arch/arm/dts/socfpga.dtsi | 3 --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - arch/arm/dts/stv0991.dts | 4 ---- doc/device-tree-bindings/spi/spi-cadence.txt | 28++++++++++++++++++++++++++
Quoted 47 lines
4 files changed, 28 insertions(+), 8 deletions(-) create mode 100644
doc/device-tree-bindings/spi/spi-cadence.txtarch/arm/dts/socfpga.dtsi +0
-3@@ -636,9 +636,6 @@ <0xffa00000 0x1000>; interrupts = <0 151 4>; clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <128>; sram-size = <128>; bus-num = <2>; status = "disabled"; diff --git
a/arch/arm/dts/socfpga_cyclone5_socrates.dtsb/arch/arm/dts/socfpga_cyclone5_socrates.dts
index ea30483..557787b 100644arch/arm/dts/socfpga_cyclone5_socrates.dts +0
-1@@ -56,7 +56,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>;arch/arm/dts/stv0991.dts index renamed from arch/arm/dts/stv0991.dts +0
-0556df82..601148e 100644
arch/arm/dts/stv0991.dts +0
-3@@ -32,9 +32,6 @@ reg = <0x80203000 0x100>, <0x40000000 0x1000000>; clocks = <3750000>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <256>; sram-size = <256>; bus-num = <0>; status = "okay"; @@ -48,7 +45,6 @@m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */Quoted 1 line
- read-delay = <4>; /* delay value in read data capture
register */
Quoted 13 lines
tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>; diff --git
a/doc/device-tree-bindings/spi/spi-cadence.txtb/doc/device-tree-bindings/spi/spi-cadence.txt
new file mode 100644
index 0000000..c1e2233doc/device-tree-bindings/spi/spi-cadence.txt new file +3
-0@@ -0,0 +1,28 @@ +Cadence QSPI controller device tree bindings +-------------------------------------------- +
Quoted 8 lines
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 6 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +6
-0+Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.? bus-num
It is not being used in the cadence_qspi driver but used on socfpga arch to distinguish between different spi peripherals.
Stefan,
Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi"
Rgds,
Vikas
Quoted 25 lines
Quoted 11 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +10
-0+- status : enable in requried dts. + +connected flash properties +-------------------------- + +- spi-max-frequency : Max supported spi frequency. +- page-size : Flash page size. +- block-size : Flash memory block size. +- tshsl-ns : Added delay in master reference clocks (ref_clk) for + the length that the master mode chip select outputsdoc/device-tree-bindings/spi/spi-cadence.txt
Quoted 10 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-1+ are de-asserted between transactions. +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one + chip select being de-activated and the activation of + another. +- tchsh-ns : Delay in master reference clocks between last bit of + current transaction and de-asserting the device chip + select (n_ss_out). +- tslch-ns : Delay in master reference clocks between setting + n_ss_out low and first bit transfer --thanks!
--
Jagan | openedev.
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Hi Vikas,
Quoted 12 lines · Vikas MANOCHA
Quoted 11 lines
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 9 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-0+Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.? bus-num
Quoted 6 lines
It is not being used in the
cadence_qspidriver but used on socfpga arch to distinguish between different spi peripherals.Stefan,
Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi"
Not sure. Why do we need to remove it? I would prefer to keep it as its know to work this way.
BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some time. At least in regard to the device-tree properties. The driver has been posted for quite some time now. And I hope it will be accepted soon. And as you can see from [1] the bindings / properties differ a bit from our currently used ones. So once this driver is accepted in kernel.org, we need to re-sync the bindings / dts files again.
Thanks,
Stefan
[1] http://permalink.gmane.org/gmane.linux.drivers.mtd/58159
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Hi Jagan,
Quoted 33 lines
-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Thursday, July 02, 2015 3:12 AM
To: Vikas MANOCHA; Jagan Teki
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi:cadence_qspi: add device tree binding docHi Vikas,
Quoted 12 lines · Vikas MANOCHA
Quoted 11 lines
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 9 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-0+Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.? bus-num
Quoted 6 lines
It is not being used in the
cadence_qspidriver but used on socfpga arch to distinguish between different spi peripherals.Stefan,
Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi"Not sure. Why do we need to remove it? I would prefer to keep it as its know to work this way.
Quoted 6 lines
BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some time. At least in regard to the device-tree properties. The driver has been posted for quite some time now. And I hope it will be accepted soon. And as you can see from [1] the bindings / properties differ a bit from our currently used ones. So once this driver is accepted in kernel.org, we need to re-sync the bindings / dts files again.
Jagan, do you agree not to remove it ?
Rgds,
Vikas
Quoted 5 lines
Thanks,
Stefan[1] http://permalink.gmane.org/gmane.linux.drivers.mtd/58159
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Quoted 35 lines · Vikas MANOCHA
Hi Jagan,
Quoted 33 lines
-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Thursday, July 02, 2015 3:12 AM
To: Vikas MANOCHA; Jagan Teki
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi:cadence_qspi: add device tree binding docHi Vikas,
Quoted 12 lines · Vikas MANOCHA
Quoted 11 lines
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 9 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-0+Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.? bus-num
Quoted 6 lines
It is not being used in the
cadence_qspidriver but used on socfpga arch to distinguish between different spi peripherals.Stefan,
Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi"Not sure. Why do we need to remove it? I would prefer to keep it as its know to work this way.
Quoted 8 lines
Quoted 6 lines
BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some time. At least in regard to the device-tree properties. The driver has been posted for quite some time now. And I hope it will be accepted soon. And as you can see from [1] the bindings / properties differ a bit from our currently used ones. So once this driver is accepted in kernel.org, we need to re-sync the bindings / dts files again.
Jagan, do you agree not to remove it ?
Yes, but one think you can do is just add what ever nodes required on your dts and document the same - don't touch dtsi.
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v3 10/10 spi: cadence_qspi: add device tree binding doc
Thanks Jagan,
Quoted 51 lines
-----Original Message-----
From: Jagan Teki [mailto:jteki at openedev.com]
Sent: Thursday, July 02, 2015 10:49 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot at lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi:cadence_qspi: add device tree binding docQuoted 42 lines · Vikas MANOCHA
Hi Jagan,
Quoted 39 lines
-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de]
Sent: Thursday, July 02, 2015 3:12 AM
To: Vikas MANOCHA; Jagan Teki
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi:cadence_qspi: add device tree binding docHi Vikas,
Quoted 12 lines · Vikas MANOCHA
Quoted 11 lines
doc/device-tree-bindings/spi/spi-cadence.txt line 9
Quoted 9 lines
doc/device-tree-bindings/spi/spi-cadence.txt new file +9
-0+Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size.? bus-num
Quoted 6 lines
It is not being used in the
cadence_qspidriver but used on socfpga arch to distinguish between different spi peripherals.Stefan,
Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi"Not sure. Why do we need to remove it? I would prefer to keep it as its know to work this way.
BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some time. At least in regard to the device-tree properties. The driver has been posted for quite some time now. And I hope it will be accepted soon. And as you can see from [1] the bindings / properties differ a bit from our currently used ones. So once this driver is accepted in kernel.org, we need to re-sync the bindings / dts files again.
Quoted 4 lines
Quoted 1 line
Jagan, do you agree not to remove it ?
Yes, but one think you can do is just add what ever nodes required on your dts and document the same - don't touch dtsi.
Makes sense, will do it.
Rgds,
Vikas
Quoted 4 lines
thanks!
--
Jagan | openedev.